UT1553B RTR Remote Terminal with RAM
F
EATURES
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Complete MIL-STD-1553B remote terminal interface
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1K x 16 of on-chip static RAM for message data,
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completely accessible to host
Self-test capability, including continuous loop-back
compare
Programmable memory mapping via pointers for
efficient use of internal memory, including buffering
multiple messages per subaddress
RT-RT Terminal Address Compare
Command word stored with incoming data for
enhanced data management
User selectable RAM Busy (RBUSY) signal for slow
or fast processor interfacing
Full military operating temperature range, -55°C to
+125°C, screened to the specific test methods listed in
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Table I of MIL-STD-883, Method 5004, Class B, also
Standard Military Drawing available
Available in 68-pin pingrid array package
I
NTRODUCTION
The UT1553B RTR is a monolithic CMOS VLSI solution
to the requirements of the dual-redundant MIL-STD-1553B
interface. Designed to reduce cost and space, the RTR
integrates the remote terminal logic with a user-configured
1K x 16 static RAM. In addition, the RTR has a flexible
subsystem interface to permit use with most processors or
controllers.
The RTR provides all protocol, data handling, error
checking, and memory control functions, as well as
comprehensive self-test capabilities. The RTR’s memory
meets all of MIL-STD-1553B message storage needs
through user-defined memory mapping. This memory-
mapped architecture allows multiple message buffering at
MCSA(4:0)
MODE CODE/
SUBADDRESS
OUTPUT MULTIPLEXING AND
SELF-TEST WRAPAROUND LOGIC
OUT
RTA(4:0)
REMOTE TERMINAL
ADDRESS
CONTROL
INPUTS
STATUS
OUTPUTS
DECODER
COMMAND
RECOGNITION
CONTROL AND
ERROR LOGIC
1K X 16 RAM
ADDR(9:0)
MUX
ENCODER
PTR REGISTER
IN
OUT
DECODER
IN
12MHz
DATA(15:0)
2MHz
RESET
Figure 1. UT1553B RTR Functional Block Diagram
RTR-1
Table of Contents
1.0
ARCHITECTURE AND OPERATION.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Memory Map and Host Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 RTR RAM Pointer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.4 Mode Code and Subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.5 MIL-STD-1553B Subaddress and Mode Codes . . . . . . . . . . . . . . . . . . . . . . . . .9
1.6 Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.7 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.8 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.9 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.10 RT-RT Transfer Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.11 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
MEMORY MAP EXAMPLE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.0
3.0
PIN IDENTIFICATION AND DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.0
MAXIMUM AND RECOMMENDED OPERATING CONDITIONS.
. . . . . . . . . . . . . . . . 19
5.0
DC ELECTRICAL CHARACTERISTICS
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6.0
AC ELECTRICAL CHARACTERISTICS.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.0
PACKAGE OUTLINE DRAWING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
RTR-2
1.0 A
RCHITECTURE
A
ND
O
PERATION
The UT1553B RTR is an interface device linking a MIL-
STD-1553 serial data bus and a host microprocessor system.
The RTR’s MIL-STD-1553B interface includes encoding/
decoding logic, error detection, command recognition, 1K
x 16 of SRAM, pointer registers, clock, and reset circuits.
alert the host. The RBUSY signal is programmable via the
internal Control Register to be asserted either 5.7ms or
2.7ms prior to the RTR needing access to its internal RAM.
The RTR stores MIL-STD-1553B messages in 1K x 16 of
on-chip RAM. For efficient use of the 1K x 16 memory on
the RTR, the host programs a set of pointers to map where
the 1553B message is stored. The RTR uses the upper 64
words (address 3C0 (hex) through 3FF (hex)) as pointers.
The RTR provides pointers for all 30 receive subaddresses,
all 30 transmit subaddresses, and four mode code
commands with associated data words as defined in MIL-
STD-1553B. The remaining 960 words of memory
contain receive, transmit, and mode code data in a
host-defined structure.
1.1 Memory Map and Host Memory Interface
The host can access the 1K x 16 RAM memory like a
standard RAM device through the 10-bit address and 16-bit
data buses. The host uses the Chip Select (CS), Read/Write
(RD/WR), and Output Enable (OE) signals to control data
transfer to and from memory. When the RTR requires access
to its own internal RAM, it asserts the RBUSY signal to
RTR Memory Map
Message
Storage
Locations
000 (hex)
3BF(hex)
15 MSB
XMIT VECTOR WORD MODE CODE (W/DATA)
Receive
Message
Pointers
(3C1 TO 3DE)
RCV SUBADDRESS 30
SYNCHRONIZE MODE CODE (W/DATA)
15 MSB
0 LSB
3DE (hex)
3DF (hex)
RCV SUBADDRESS 01
0 LSB
3C0 (hex)
3C1 (hex)
Transmit
Message
Pointers
(3E1 TO 3FE)
XMIT LAST COMMAND MODE CODE (W/DATA)
XMT SUBADDRESS 01
3E0 (hex)
3E1 (hex)
XMT SUBADDRESS 30
XMT BIT WORD MODE CODE (W/DATA)
15 MSB
Figure 2. RTR Memory Map
0 LSB
3FE (hex)
3FF (hex)
RTR-3
MESSAGE INDEX
15 (MSB)
Message index: Defines the
maximum messages buffered for
the given subaddresses.
10
9
MESSAGE DATA ADDRESSES
0 (LSB)
Message Data Address:
Indicates the starting memory address for incoming
message storage.
Figure 3. Message Pointer Structure
1.2 RTR RAM Pointer Structure
The RAM 16-bit pointers have a 6-bit index field and a
10-bit address field. The 6-bit index field allows for the
storage of up to 64 messages per subaddress. A message
consists of the 1553 command word and its associated data
words.
The 16-bit pointer for Transmit Last Command Mode Code
is located at memory location 3E0 (hex). The Transmit Last
Command Mode Code pointer buffers up to 63 command
words. An example of command word storage follows:
Example:
3E0 (hex)
Contents = FC00 (hex)
11 1111 00 0000 0000
Address Field = 000 (hex)
Index Field = 3F (hex)
First command word storage location (3E0=F801):
Address Field = 001 (hex)
Index Field = 3E (hex)
Sixty-third command word storage location (3E0=003F):
Address Field = 03F (hex)
Index Field = 00 (hex)
Sixty-fourth command word storage location (3E0=003F)
(previous command word overwritten):
Address Field = 03F (hex)
Index Field = 00 (hex)
The Transmit Last Command Mode Code has Address Field
boundary conditions for the location of command word
buffers. The host can allocate a maximum 63 sequential
locations following the Address Field starting address. For
proper operation, the Address Field must start on an I x 40
(hex) address boundary, where I is greater than or equal to
zero and less than or equal to 14. A list of valid Index and
Address Fields follows:
I
0
1
2
3
4
5
6
7
8
9
Valid Index Fields
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
3F (hex) to 00 (hex)
Valid Address Fields
000 (hex) to 03F (hex)
040 (hex) to 07F (hex)
080 (hex) to 0BF (hex)
0C0 (hex) to 0FF (hex)
100 (hex) to 13F (hex)
140 (hex) to 17F (hex)
180 (hex) to 1BF (hex)
1C0 (hex) to 1FF (hex)
200 (hex) to 23F (hex)
240 (hex) to 27F (hex)
280 (hex) to 2BF (hex)
2C0 (hex) to 2FF (hex
300 (hex) to 33F (hex)
340 (hex) to 37F (hex)
380 (hex) to 3BF (hex)
10 3F (hex) to 00 (hex)
11 3F (hex) to 00 (hex)
12 3F (hex) to 00 (hex)
13 3F (hex) to 00 (hex)
14 3F (hex) to 00 (hex)
RTR-4
Subaddress/Mode Code
RAM Location
Subaddress/Mode Code
RAM Location
Transmit Vector Word Mode Code
Receive Subaddress
01
Receive Subaddress
02
Receive Subaddress
03
Receive Subaddress
04
Receive Subaddress
05
Receive Subaddress
06
Receive Subaddress
07
Receive Subaddress
08
Receive Subaddress
09
Receive Subaddress
10
Receive Subaddress
11
Receive Subaddress
12
Receive Subaddress
13
Receive Subaddress
14
Receive Subaddress
15
Receive Subaddress
16
Receive Subaddress
17
Receive Subaddress
18
Receive Subaddress
19
Receive Subaddress
20
Receive Subaddress
21
Receive Subaddress
22
Receive Subaddress
23
Receive Subaddress
24
Receive Subaddress
25
Receive Subaddress
26
Receive Subaddress
27
Receive Subaddress
28
Receive Subaddress
29
Receive Subaddress
30
Synchronize w/Data Word Mode Code
3C0 (hex)
3C1 (hex)
3C2 (hex)
3C3 (hex)
3C4 (hex)
3C5 (hex)
3C6 (hex)
3C7 (hex)
3C8 (hex)
3C9 (hex)
3CA (hex)
3CB (hex)
3CC (hex)
3CD (hex)
3CE (hex)
3CF (hex)
3D0 (hex)
3D1 (hex)
3D2 (hex)
3D3 (hex)
3D4 (hex)
3D5 (hex)
3D6 (hex)
3D7 (hex)
3D8 (hex)
3D9 (hex)
3DA (hex)
3DB (hex)
3DC (hex)
3DD (hex)
3DE (hex)
3DF (hex)
Transmit Last Command Mode Code
Transmit Subaddress
01
Transmit Subaddress
02
Transmit Subaddress
03
Transmit Subaddress
04
Transmit Subaddress
05
Transmit Subaddress
06
Transmit Subaddress
07
Transmit Subaddress
08
Transmit Subaddress
09
Transmit Subaddress
10
Transmit Subaddress
11
Transmit Subaddress
12
Transmit Subaddress
13
Transmit Subaddress
14
Transmit Subaddress
15
Transmit Subaddress
16
Transmit Subaddress
17
Transmit Subaddress
18
Transmit Subaddress
19
Transmit Subaddress
20
Transmit Subaddress
21
Transmit Subaddress
22
Transmit Subaddress
23
Transmit Subaddress
24
Transmit Subaddress
25
Transmit Subaddress
26
Transmit Subaddress
27
Transmit Subaddress
28
Transmit Subaddress
29
Transmit Subaddress
30
Transmit Bit Word Mode Code
3E0 (hex)
3E1 (hex)
3E2 (hex)
3E3 (hex)
3E4 (hex)
3E5 (hex)
3E6 (hex)
3E7 (hex)
3E8 (hex)
3E9 (hex)
3EA (hex)
3EB (hex)
3EC (hex)
3ED (hex)
3EE (hex)
3EF (hex)
3F0 (hex)
3F1 (hex)
3F2 (hex)
3F3 (hex)
3F4 (hex)
3F5 (hex)
3F6 (hex)
3F7 (hex)
3F8 (hex)
3F9 (hex)
3FA (hex)
3FB (hex)
3FC (hex)
3FD (hex)
3FE (hex)
3FF (hex)
1.3 Internal Registers
The RTR uses two internal registers to allow the host to
control the RTR operation and monitor its status. The host
uses the Control (CTRL) signal along with Chip Select (CS),
Read/Write (RD/WR), and Output Enable (OE) to read the
16-bit Status Register or write to the 11-bit Control Register.
No address data is needed to select a register.
The Control Register toggles bits in the MIL-STD-1553B
status word, enables the biphase inputs, recognizes
broadcast commands, determines RAM Busy (RBUSY)
timing, selects terminal active flag, and puts the part in self-
test mode. The Status Register supplies operational status
of the UT1553B RTR to the host. These registers must be
initialized before attempting RTR operation. Internal
registers can be accessed while RBUSY is active.
RTR-5
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