3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Features
256K x 16 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise.
Equal access and cycle times
– Commercial and Industrial: 10/12/15ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
Available in 44-pin, 400 mil plastic SOJ package and a 44-
pin, 400 mil TSOP Type II package and a 48 ball grid array,
9mm x 9mm package.
IDT71V416YS
IDT71V416YL
Description
The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized
as 256K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V416 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V416 are LVTTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mm package.
x
x
x
x
x
x
x
x
x
Functional Block Diagram
Output
Enable
Buffer
OE
A0 - A17
Address
Buffers
Row / Column
Decoders
8
CS
Chip
Select
Buffer
8
Sense
Amps
and
Write
Drivers
High
Byte
Output
Buffer
High
Byte
Write
Buffer
8
I/O 1
8
I/O 8
4,194,304-bit
Memory
Array
WE
Write
Enable
Buffer
16
8
Low
Byte
Output
Buffer
Low
Byte
Write
Buffer
8
I/O 7
8
8
I/O 0
BHE
Byte
Enable
Buffers
BLE
6442 drw 01
OCTOBER 2003
1
©2003 Integrated Device Technology, Inc.
DSC-6442/00
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations - SOJ/TSOP
A0
A1
A2
A3
A4
CS
I/O 0
I/O 1
I/O 2
I/O 3
V
DD
V
SS
I/O 4
I/O 5
I/O 6
I/O 7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
I/O 15
I/O 14
I/O 13
I/O 12
V
SS
V
DD
I/O 11
I/O 10
I/O 9
I/O 8
NC*
A14
A13
A12
A11
A10
Pin Configurations - 48 BGA
1
A
B
C
D
E
F
G
H
BLE
I/O
0
I/O
1
V
SS
V
DD
I/O
6
I/O
7
NC
2
OE
BHE
I/O
2
I/O
3
I/O
4
I/O
5
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CS
I/O
10
I/O
11
I/O
12
I/O
13
WE
A
11
6
NC
I/O
8
I/O
9
V
DD
V
SS
I/O
14
I/O
15
NC
6442 tbl 11
SO44-1
SO44-2
6442 drw 02
*Pin 28 can either be a NC or connected to Vss
Top View
Pin Descriptions
A
0
- A
17
CS
WE
OE
BHE
BLE
I/O
0
- I/O
15
V
DD
V
SS
Address Inputs
Chip Select
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
Input
Input
I/O
Pwr
Gnd
6442 tbl 01
SOJ Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
8
Unit
pF
pF
6442 tbl 02
48 BGA Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
6
7
Unit
pF
pF
6442 tbl 02b
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
2
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
DD
V
IN,
V
OUT
T
BIAS
T
STG
P
T
I
OUT
Rating
Supply Voltage Relative to
V
SS
Terminal Voltage Relative to
V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +4.6
-0.5 to V
DD
+0.5
-55 to +125
-55 to +125
1
50
Unit
V
V
o
o
Recommended Operating
Temperature and Supply
Voltage
Grade
Commercial
Industrial
Temperature
0
O
C to +70
O
C
–40
O
C to +85
O
C
V
SS
0V
0V
V
DD
See Below
See Below
6442 tbl 05
C
C
W
mA
6442 tbl 04
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(2)
Typ.
3.3
0
____
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Max.
3.6
0
V
DD
+0.3
(1)
0.8
Unit
V
V
V
V
6442 tbl 06
____
NOTES:
1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
Truth Table
(1)
CS
H
L
L
L
L
L
L
L
L
OE
X
L
L
L
X
X
X
H
X
WE
X
H
H
H
L
L
L
H
X
BLE
X
L
H
L
L
L
H
X
H
BHE
X
H
L
L
L
H
L
X
H
I/O
0-
I/O
7
High-Z
DATA
OUT
High-Z
DATA
OUT
DATA
IN
DATA
IN
High-Z
High-Z
High-Z
I/O
8-
I/O
15
High-Z
High-Z
DATA
OUT
DATA
OUT
DATA
IN
High-Z
DATA
IN
High-Z
High-Z
Function
Deselected - Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
6442 tbl 03
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
6.42
3
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V416
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= Max., V
IN =
V
SS
to V
DD
V
DD
= Max.,
CS
= V
IH
, V
OUT
= V
SS
to V
DD
I
OL
= 8mA, V
DD
= Min.
I
OH
= -4mA, V
DD
= Min.
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
6442 tbl 07
2.4
DC Electrical Characteristics
(1, 2, 3)
(V
DD
= Min. to Max., V
LC
= 0.2V, V
HC
= V
DD
– 0.2V)
71V416S/L10
Symbol
I
CC
Parameter
Dynamic Operating Current
CS
< V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
Dynamic Standby Power Supply Current
CS
> V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
Full Standby Power Supply Current (static)
CS
> V
HC
, Outputs Open, V
DD
= Max., f = 0
(4)
S
L
S
L
S
L
Com'l.
200
180
70
50
20
10
Ind.
(5)
200
—
70
—
20
—
71V416S/L12
Com'l.
180
170
60
45
20
10
Ind.
180
170
60
45
20
10
71V416S/L15
Com'l.
170
160
50
40
20
10
Ind.
170
160
50
40
20
10
6442 tbl 08
Unit
mA
I
SB
mA
I
SB1
mA
NOTES:
IDT71V416S/71V416L
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and V
DD
-0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
AC Test Loads
+1.5V
50Ω
I/O
Z
0
= 50Ω
30pF
6442 drw 03
3.3V
320Ω
DATA
OUT
5pF*
350Ω
6442 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW
, and t
WHZ
)
7
6
∆t
AA,
t
ACS
(Typical, ns) 5
4
3
2
1
•
•
•
•
•
•
•
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
Figures 1,2 and 3
6442 tbl 09
8 20 40 60 80 100 120 140 160 180 200
CAPACITANCE (pF)
6442 drw 05
Figure 3. Output Capacitive Derating
6.42
4
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
71V416S/L10
(2)
Symbol
READ CYCLE
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
BE
t
BLZ
(1)
t
BHZ
(1)
WRITE CYCLE
t
WC
t
AW
t
CW
t
BW
t
AS
t
WR
t
WP
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
Address Hold from End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
10
8
8
8
0
0
8
5
0
3
____
____
71V416S/L12
Min.
Max.
71V416S/L15
Min.
Max.
Unit
Parameter
Min.
Max.
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
10
____
____
12
____
____
15
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
____
12
12
____
15
15
____
____
____
____
4
____
4
____
4
____
5
5
____
6
6
____
7
7
____
____
____
____
0
____
0
____
0
____
5
____
6
____
7
____
4
____
4
____
4
____
5
____
6
____
7
____
0
____
0
____
0
____
5
6
7
12
8
8
8
0
0
8
6
0
3
____
____
15
10
10
10
0
0
10
7
0
3
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6442 tbl 10
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
6
7
7
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. Low power 10ns (L10) speed 0ºC to +70ºC temperature range only.
Timing Waveform of Read Cycle No. 1
(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
6442d06
DATA
OUT
VALID
t
OH
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3.
OE, BHE,
and
BLE
are LOW.
6.42
5
FPGA/CPLD
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