TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
7.
8.
9.
GENERAL DESCRIPTION ................................................................................................................ 1
FEATURES ........................................................................................................................................ 1
ORDERING INFORMATION ............................................................................................................. 1
BLOCK DIAGRAM ............................................................................................................................ 2
SSD1881Z DIE PAD ASSIGNMENT ................................................................................................. 3
SSD1881TR TAB PIN ASSIGNMENT............................................................................................... 6
SSD1881T1R1 TAB PIN ASSIGNMENT........................................................................................... 8
SSD1881T2R TAB PIN ASSIGNMENT........................................................................................... 10
PIN DESCRIPTION.......................................................................................................................... 12
VDD_ROW, +V1, VC, -V1 (Power Pin) ................................................................................................ 12
YD (Input Pin) ....................................................................................................................................... 12
LP (Input Pin)........................................................................................................................................ 12
FR (Input Pin) ....................................................................................................................................... 12
F1, F2 (Input Pin) .................................................................................................................................. 12
DOFF# (Input Pin) ................................................................................................................................ 12
SEL (Input Pin) ..................................................................................................................................... 12
CIO1, CIO2 (I/O Pin) ............................................................................................................................. 12
SHL (Input Pin) ..................................................................................................................................... 13
LSEL (Input Pin) ................................................................................................................................... 13
CSEL (Input Pin)................................................................................................................................... 13
TEST1 (Input Pin) ................................................................................................................................. 13
TEST2 (Input Pin, only exists on gold-bumped die)......................................................................... 13
COM0-COM159 (Output Pin) ............................................................................................................... 13
NCx and DUMCORx (Dummy Pin) ...................................................................................................... 13
10.
FUNCTIONAL BLOCK DESCRIPTIONS ........................................................................................ 14
Controller and Data Register .............................................................................................................. 14
Bi-directional Shift Register ............................................................................................................... 14
Common Cell Level Shifter ................................................................................................................. 14
Timing Diagram For 1/160 duty and 1P operation (DOFF# = H and FR=L) .................................... 15
Timing Diagram For 1/160 duty and 1P operation (DOFF# = H and FR=H).................................... 16
Timing Diagram For 1/160 duty and 1/2P operation (DOFF# = H and FR = L) ............................... 17
Timing Diagram For 1/160 duty and 1/2P operation (DOFF# = H and FR = H)............................... 18
11.
12.
13.
MAXIMUM RATINGS....................................................................................................................... 19
DC CHARACTERISTICS................................................................................................................. 20
AC CHARACTERISTICS................................................................................................................. 21
Input Timing Characteristics .............................................................................................................. 21
Output Timing Characteristics ........................................................................................................... 22
14.
15.
16.
PRECAUTION.................................................................................................................................. 23
APPLICATION EXAMPLE – 160 X 160 LCD SYSTEM.................................................................. 25
PACKAGE DIMENSION .................................................................................................................. 26
SOLOMON
SOLOMON SYSTECH LIMITED
SEMICONDUCTOR TECHNICAL DATA
SSD1881
Advance Information
SSD1881 MLA ROW (COMMON) DRIVER
CMOS
1. GENERAL DESCRIPTION
The SSD1881 is an MLA (Multi Line Addressing), 160 outputs and triple-value low resistance common driver. Joining with the
SSD1730 MLA power chip and the SSD1870 column driver, an MLA LCD module system having high picture quality, high
speed responses and low power consumption can be produced. SSD1881 can be configured as 140 outputs or 160 outputs.
2. FEATURES
Power supply to logic system, 2.7V - 5.5V
LCD drive voltage, 14V - 30V
140 or 160 common outputs
Drive duty, 1/160 and 1/320
1/2P and 1P operation mode
Adjustable LCD power source offset bias
Non-biased display off function
Seletable output shift direction
Cascade supported
Available in Gold-bumped die and TAB (Tape Automated Bonding) Package
3. ORDERING INFORMATION
Ordering Part
Number
Output lead pitch
(mm)
Package Form
SSD1881Z
N/A
SSD1881TR
0.2295
SSD1881T1R1
0.14
SSD1881T2R
0.22
Table 1 - Ordering part number
Gold Bump Die
TAB
TAB
TAB
This document contains information on a new product. Specifications and information herein are subject to change without notice.
IC manufactured under Motif license including U.S. Patent No. 5,420,604
Copyright
2001
SOLOMON Systech Limited
Rev 2.1
09/2002
4. BLOCK DIAGRAM
COM0 ~ COM159
VDD_ROW
V
SS
Common Cell
Level Shifter
+V
1
V
C
-V
1
DOFF#
TEST1
FR
F1
F2
LP
Controller
Data Register
160 bits
CIO1
YD
Bi-directional Shift Register
40 bits
CIO2
SHL
SEL
LSEL
CSEL
Figure 1 - Block Diagram of SSD1881
SOLOMON
Rev 2.1
09/2002
SSD1881
2
5. SSD1881Z DIE PAD ASSIGNMENT
DUMCOR2
DUMCOR1
NC35
NC34
NC33
NC32
NC31
NC30
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
COM97
COM98
COM99
COM100
COM101
COM102
COM103
COM104
COM105
COM106
COM107
COM108
COM109
COM110
COM111
COM112
COM113
COM114
COM115
COM116
COM117
COM118
COM119
COM120
COM121
COM122
COM123
COM124
COM125
COM126
COM127
COM128
COM129
COM130
COM131
COM132
COM133
COM134
COM135
COM136
COM137
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
NC29
NC28
NC27
+V
1
+V
1
+V
1
VC
VC
VC
-V
1
-V
1
-V
1
NC26
NC25
NC24
NC23
NC22
NC21
NC20
NC19
NC18
NC17
NC16
TEST2
TEST1
F2
F2
F1
F1
YD
YD
CIO1
CIO1
CIO2
CIO2
LP
LP
CSEL
FR
DOFF#
LSEL
VDD_ROW
VDD_ROW
VDD_ROW
SEL
SHL
NC15
NC14
NC13
NC12
NC11
NC10
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
-V
1
-V
1
-V
1
VC
VC
VC
+V
1
+V
1
+V
1
NC1
COM159
COM158
COM157
COM156
COM155
COM154
COM153
COM152
COM151
COM150
COM149
COM178
COM147
COM146
COM145
COM144
COM143
COM142
COM141
COM140
COM139
COM138
Gold Bump Alignment Mark
This alignment mark contains gold bump for
IC bumping process alignment and IC
identifications. No conductive tracks should
be laid underneath this mark to avoid short
circuit.
Die Size: 12233.7um X 1356.1um
Bump Size: 60.2um X 60.2um
Die Thickness: 533um
Center: 2389.675, -280.8
Size: 94.5um x 94.5um
Y
X
Center: -1749.825,-305.25
Size: 70um x 70um
SSD1881
Pad 1,2,3.......116
Center: -2254.575,-272.225
Size: 26.8um x 27.2um
Center: -2497.65, -280.8
Size: 94.5um x 94.5um
Pad #1
NC36
NC37
NC38
NC39
NC40
DUMCOR3
NC41
Figure 2 – SSD1881Z Die Pad Assignment
DUMCOR4
SSD1881
3
Rev 2.1
09/2002
SOLOMON