S-8233B Series
www.sii-ic.com
© Seiko Instruments Inc., 1997-2013
BATTERY PROTECTION IC
FOR 3-SERIAL-CELL PACK
Rev.5.1
_00
The S-8233B is a series of lithium-ion rechargeable battery protection ICs incorporating high-accuracy (±25 mV)
voltage detection circuits and delay circuits. It is suitable for a 3-serial-cell lithium-ion rechargeable battery
pack.
Features
(1)
Internal high-accuracy voltage detection circuit
•
Overcharge detection voltage
3.80
±
0.025 V to 4.40
±
0.025 V
5 mV - step
•
Overcharge release voltage
3.45
±
0.100 V to 4.40
±
0.100 V
5 mV - step
(The overcharge release voltage can be selected within the range where a difference from
overcharge detection voltage is 0 to 0.35 V with 50 mV - step)
•
Overdischarge detection voltage
2.00
±
0.08 V to 2.80
±
0.08 V
50 mV - step
•
Overdischarge release voltage
2.00
±
0.10 V to 4.00
±
0.10 V
50 mV - step
(The overdischarge release voltage can be selected within the range where a difference from
overdischarge detection voltage is 0 to 1.2 V with 50 mV - step)
•
Overcurrent detection voltage 1
0.15
±
0.015 V to 0.5
±
0.05 V
50 mV - step
High input-voltage device (absolute maximum rating: 26 V)
Wide operating voltage range:
2 V to 24 V
The delay time for every detection can be set via an external capacitor.
Three overcurrent detection levels (protection for short-circuiting)
Internal charge/discharge prohibition circuit via the control pin
The function for charging batteries from 0 V is available.
Low current consumption
•
Operation
50
μA
max. (+25°C)
•
Power-down
0.1
μA
max. (+25°C)
Lead-free, Sn 100%, halogen-free
*1
Product Name Structure”
for details.
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
*1.
Refer to “
Applications
•
Lithium-ion rechargeable battery packs
•
Lithium polymer rechargeable battery packs
Package
•
16-Pin TSSOP
Seiko Instruments Inc.
1
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233B Series
Block Diagram
Rev.5.1
_00
VCC
Reference
voltage 1
Overcurrent 2,3
delay circuit
Overcurrent
detection
circuit
VMP
+
−
CD1
Battery 1
Overcharge
+
−
Battery 1
Overdischarge
Overcurrent1,
delay circuit
COVT
VC1
Battery 1
Overcharge
+
−
Battery 2
Overcharge
Overdischarge
delay circuit
CDT
Control
Logic
Overcharge
delay circuit
CD2
+
Battery 2
Overdischarge
Reference
voltage 2
−
CCT
VC2
Battery 2
Overcharge
+
−
Battery 3
Overcharge
DOP
CD3
+
Battery 3
Overdischarge
Reference
voltage 3
−
COP
VSS
Battery 3
Overcharge
Floating
detection circuit
CTL
Remark
The delay time for overcurrent detection 2 and 3 is fixed by an internal IC circuit. The delay time
cannot be changed via an external capacitor.
Figure 1
2
Seiko Instruments Inc.
Rev.5.1
_00
Product Name Structure
1. Product name
BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK
S-8233B Series
S-8233B
x
FT
−
TB
−
x
Environmental code
U : Lead-free (Sn 100%), halogen-free
G : Lead-free (for details, please contact our sales office)
IC direction in tape specifications
*1
Package name (abbreviation)
FT: 16-Pin TSSOP
Serial code
Assigned from A to Z in alphabetical order
*1.
Refer to the tape specifications.
2. Package
Package Name
16-Pin TSSOP
Drawing Code
Tape
FT016-A-C-SD
Package
FT016-A-P-SD
Reel
FT016-A-R-SD
3. Product name list
Table 1
Overcharge
Product name / detection
Item
voltage
V
CU
S-8233BAFT-TB-x
S-8233BBFT-TB-x
S-8233BCFT-TB-x
S-8233BDFT-TB-x
S-8233BEFT-TB-x
S-8233BFFT-TB-U
4.225 V
4.325 V
4.200 V
4.325 V
4.080 V
4.200 V
Overcharge Overdischarge
0V
Overcurrent
Overdischarge
release
detection
detection battery Conditioning CTL
release voltage
voltage
voltage
voltage1 charging function
logic
*1
V
DU
V
CD
V
DD
function
V
IOV1
4.225 V
4.150 V
4.200 V
4.150 V
3.900 V
4.050 V
2.30 V
2.30 V
2.80 V
2.00 V
2.50 V
2.40 V
2.70 V
2.70 V
3.30 V
2.70 V
2.75 V
2.70 V
0.20 V
0.20 V
0.25 V
0.50 V
0.20 V
0.30 V
−
−
Available
−
Available
Available
Available
Unavailable
Available
Unavailable
Available
Available
normal
reverse
normal
reverse
normal
normal
*1.
The input voltage of CTL for normal status is changed by the CTL logic. (Please refer to
“Operation”).
Remark 1.
Please contact our sales office for the products with the detection voltage value other than those
specified above.
2.
x: G or U
3.
Please select products of environmental code = U for Sn 100%, halogen-free products.
Seiko Instruments Inc.
3
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233B Series
Rev.5.1
_00
Pin Configuration
16-Pin TSSOP
Top view
DOP
NC
COP
VMP
COVT
CDT
CCT
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
NC
CD1
VC1
CD2
VC2
CD3
CTL
Table 2
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
DOP
NC
COP
VMP
COVT
CDT
CCT
VSS
CTL
CD3
VC2
CD2
VC1
CD1
NC
VCC
Non connect
*1
Connects FET gate for charge control (Nch open-drain output)
Detects voltage between VCC to VMP(Overcurrent detection pin)
Connects capacitor for overcurrent detection1delay circuit
Connects capacitor for overdischarge detection delay circuit
Connects capacitor for overcharge detection delay circuit
Negative power input, and connects negative voltage for battery 3
Charge/discharge control signal input
Battery 3 conditioning signal output
Connects battery 2 negative voltage and battery 3 positive voltage
Battery 2 conditioning signal output
Connects battery 1 negative voltage and battery 2 positive voltage
Battery 1 conditioning signal output
Non connect
*1
Positive power input and connects battery 1 positive voltage
Description
Connects FET gate for discharge control (CMOS output)
Figure 2
*1.
The NC pin is electrically open. The NC pin can be connected to VCC or VSS.
4
Seiko Instruments Inc.
Rev.5.1
_00
BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK
S-8233B Series
Absolute Maximum Ratings
Table 3
(Ta
=
25°C unless otherwise specified)
Item
Symbol
Applied Pins
−
Absolute Maximum Ratings
V
SS
-0.3 to V
SS
+26
V
SS
-0.3 to V
CC
+0.3
V
SS
-0.3 to V
SS
+26
V
C1
-0.3 to V
CC
+0.3
V
C2
-0.3 to V
CC
+0.3
V
SS
-0.3 to V
CC
+0.3
V
SS
-0.3 to V
CC
+0.3
V
SS
-0.3 to V
VMP
+0.3
1100
*1
-20 to +70
-40 to +125
Unit
V
V
V
V
V
V
V
V
mW
°C
°C
Input voltage between VCC and VSS V
DS
Input pin voltage
VMP Input pin voltage
CD1 output pin voltage
CD2 output pin voltage
CD3 output pin voltage
DOP output pin voltage
COP output pin voltage
Power dissipation
Operating ambient temperature
V
IN
V
VMP
V
CD1
V
CD2
V
CD3
V
DOP
V
COP
P
D
T
opr
VC1, VC2, CTL,
CCT, CDT, COVT
VMP
CD1
CD2
CD3
DOP
COP
−
−
−
300 (When not mounted on board) mW
Storage temperature
T
stg
−
*1.
When mounted on board
[Mounted board]
(1) Board size : 114.3 mm
×
76.2 mm
×
t1.6 mm
(2) Board name : JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
1200
1000
800
600
400
200
0
0
50
100
150
Ambient Temperature (Ta) [°C]
Figure 3 Power Dissipation of Package (When Mounted on Board)
Power Dissipation (P
D
) [Mw]
Seiko Instruments Inc.
5
MEMS传感器
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