CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. The HIP2100 is capable of derated operation at supply voltages exceeding 14V. Figure 16 shows the high-side voltage derating curve for this
mode of operation.
4. All voltages referenced to V
SS
unless otherwise specified.
5.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
θ
JC,
the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO, Unless Otherwise Specified.
T
J
= +25°C
T
J
= -40°C TO +125°C
MIN
(Note 7)
MAX
(Note 7)
UNITS
PARAMETERS
SUPPLY CURRENTS
V
DD
Quiescent Current
V
DD
Operating Current
Total HB Quiescent Current
Total HB Operating Current
HB to V
SS
Current, Quiescent
HB to V
SS
Current, Operating
INPUT PINS
Low Level Input Voltage Threshold
High Level Input Voltage Threshold
Input Voltage Hysteresis
Input Pulldown Resistance
UNDERVOLTAGE PROTECTION
V
DD
Rising Threshold
V
DD
Threshold Hysteresis
HB Rising Threshold
HB Threshold Hysteresis
SYMBOL
TEST CONDITIONS
MIN TYP MAX
I
DD
I
DDO
I
HB
I
HBO
I
HBS
I
HBSO
LI = HI = 0V
f = 500kHz
LI = HI = 0V
f = 500kHz
V
HS
= V
HB
= 114V
f = 500kHz
-
-
-
-
-
-
0.1
1.5
0.1
1.5
0.05
0.7
0.15
2.5
0.15
2.5
1
-
-
-
-
-
-
-
0.2
3
0.2
3
10
-
mA
mA
mA
mA
µA
mA
V
IL
V
IH
V
IHYS
R
I
4
-
-
-
5.4
5.8
0.4
200
-
7
-
-
3
-
-
100
-
8
-
500
V
V
V
kΩ
V
DDR
V
DDH
V
HBR
V
HBH
7
-
6.5
-
7.3
0.5
6.9
0.4
7.8
-
7.5
-
6.5
-
6
-
8
-
8
-
V
V
V
V
4
FN4022.14
HIP2100
Electrical Specifications
V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO, Unless Otherwise Specified.
(Continued)
T
J
= +25°C
PARAMETERS
BOOT STRAP DIODE
Low-Current Forward Voltage
High-Current Forward Voltage
Dynamic Resistance
LO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
Peak Pulldown Current
HO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
Peak Pulldown Current
V
OLH
V
OHH
I
OHH
I
OLH
I
HO
= 100mA
I
HO
= -100mA, V
OHH
= V
HB
-V
HO
V
HO
= 0V
V
HO
= 12V
-
-
-
-
0.25
0.25
2
2
0.3
0.3
-
-
-
-
-
-
0.4
0.4
-
-
V
V
A
A
V
OLL
V
OHL
I
OHL
I
OLL
I
LO
= 100mA
I
LO
= -100mA, V
OHL
= V
DD
-V
LO
V
LO
= 0V
V
LO
= 12V
-
-
-
-
0.25
0.25
2
2
0.3
0.3
-
-
-
-
-
-
0.4
0.4
-
-
V
V
A
A
V
DL
V
DH
R
D
I
VDD-HB
= 100µA
I
VDD-HB
= 100mA
I
VDD-HB
= 100mA
-
-
-
0.45 0.55
0.7
0.8
0.8
1
-
-
-
0.7
1
1.5
V
V
Ω
SYMBOL
TEST CONDITIONS
MIN TYP MAX
T
J
= -40°C TO +125°C
MIN
(Note 7)
MAX
(Note 7)
UNITS
Switching Specifications
V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO, Unless Otherwise Specified.
T
J
= +25°C
T
J
= -40°C TO
+125°C
MIN
(Note 7)
-
-
-
-
-
-
-
-
-
-
-
-
MAX
(Note 7)
45
45
45
45
10
10
-
0.8
-
-
50
-
UNITS
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
PARAMETERS
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
Delay Matching: Lower Turn-On and Upper Turn-Off
Delay Matching: Lower Turn-Off and Upper Turn-On
Either Output Rise/Fall Time
Either Output Rise/Fall Time (3V to 9V)
Either Output Rise Time Driving DMOS
Either Output Fall Time Driving DMOS
Minimum Input Pulse Width that Changes the Output
Bootstrap Diode Turn-On or Turn-Off Time
NOTE:
SYMBOL
t
LPHL
t
HPHL
t
LPLH
t
HPLH
t
MON
t
MOFF
t
RC
, t
FC
t
R
, t
F
t
RD
t
FD
t
PW
t
BS
TEST
CONDITIONS
MIN TYP MAX
-
-
-
-
-
-
20
20
20
20
2
2
10
0.5
20
10
-
10
35
35
35
35
8
8
-
0.6
-
-
-
-
C
L
= 1000pF
C
L
= 0.1µF
C
L
= IRFR120
C
L
= IRFR120
-
-
-
-
-
-
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
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