DEMO MANUAL DC1826A
LTC2389
18-Bit/16-Bit, 2.5Msps Low Noise,
SAR ADCs with Pin-Configurable
Analog Input Range
DESCRIPTION
Demonstration circuit 1826A features the LTC
®
2389 low
noise, high speed successive approximation register ADC
which operates from a single 5V supply. The following
text refers to the LTC2389-18, but also applies to the
LTC2389-16, the only difference being the number of bits.
The LTC2389-18 supports pin-configurable fully differential
(±4.096V), pseudo-differential unipolar (0V to 4.096V), and
pseudo-differential bipolar (±2.048V) analog input ranges,
allowing it to interface with multiple signal chain formats.
The LTC2389-18 achieves ±2.5LSB INL (maximum), with
no missing codes at 18 bits.
The DC1826A demonstrates the performance of the
LTC2389-18 in conjunction with the DC718 QuikEval™ II
data collection board.
The demonstration circuit 1826A is intended to demon-
strate recommended grounding, component placement
and selection, routing and bypassing for this ADC. Several
suggested driver circuits for the analog inputs will be
presented.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
BOARD PHOTO
Figure 1. DC1826A Connection Diagram
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DEMO MANUAL DC1826A
DC1826A ASSEMBLY OPTIONS
ASSEMBLY VERSION
DC1826A-A
DC1826A-E
U1 PART NUMBER
LTC2389CMS-18
LTC2389CMS-16
MAX CONVERSION RATE
2.5Msps
2.5Msps
NUMBER OF BITS
18
16
SERIAL MAX CLKIN FREQUENCY
100MHz
100MHz
DC718 QUICK START PROCEDURE
Check to ensure that all switches and jumpers are set as
shown in the connection diagram of Figure 1. The default
connections configure the ADC to use the onboard refer-
ence and regulators to generate the required common
mode voltages. The analog input is DC-coupled. Connect
the DC1826A to a DC718 USB high speed data collection
board using connector J4. Then, connect the DC718 to
a host PC with a standard USB A/B cable. Apply ±9V to
the indicated terminals. Then, apply a low jitter signal
source to J2. The default setup uses a single-ended to
differential converter so that it is only necessary to apply
a single-ended input signal to J2. Connect a low jitter
2.5MHz (100MHz for serial) 3.3V
P-P
sine wave or square
wave to connector J1 for parallel operation. Note that J1
has a 49.9Ω termination resistor to ground.
Run the QuikEval II software (PScope.exe version K73 or
later) supplied with the DC718 or download it from www.
linear.com.
Complete software documentation is available from the
help menu. Updates can be downloaded from the tools
menu. Check for updates periodically as new features
may be added.
The PScope™ software should recognize the DC1826A
and configure itself automatically.
Click the collect button (see Figure 7) to begin acquiring
data. The collect button then changes to pause, which can
be clicked to stop data acquisition.
DC1826A SETUP
DC Power
The DC1826A requires ±9V
DC
and draws 100mA. Most
of the supply current is consumed by the CPLD, opamps,
regulators and discrete logic on the board. The 9V
DC
in-
put voltage powers the ADC through LT1763 regulators
which provide protection against accidental reverse bias.
Additional regulators provide power for the CPLD and
opamps. See Figure 1 for connection details.
Clock Source
You must provide a low jitter 3.3V
P-P
sine or square
wave to J1. The clock input is AC-coupled so the DC
level of the clock signal is not important. A generator
like the HP8644 or the DC1216A-A is recommended.
Even a good generator can start to produce noticeable
jitter at low frequencies. Therefore, it is recommended
for lower clock rates to divide down a higher frequency
clock to the desired sample rate. For serial operation, the
ratio of clock frequency to conversion rate is 50:1. The
maximum serial conversion rate is 2Msps. If the clock
input is to be driven with logic, it is recommended that
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DEMO MANUAL DC1826A
DC1826A SETUP
the 50Ω terminator (R6) be removed. Slow rising edges
may compromise the SNR of the converter in the presence
of high amplitude higher frequency input signals.
Data Output
Parallel data output from this board (0V to 3.3V default),
if not connected to the DC718, can be acquired by a logic
analyzer, and subsequently imported into a spreadsheet, or
mathematical package depending on what form of digital
signal processing is desired. Alternatively, the data can be
fed directly into an application circuit. Use Pin 3 of J4 to
latch the data. The data can be latched using either edge
of this signal. The data output signal levels at J4 can also
be reduced to 0V to 2.5V if the application circuit cannot
tolerate the higher voltage. This is accomplished by mov-
ing JP4 to the 2.5V position.
Reference
The default reference is the LTC2389-18’s internal 4.096V
reference. If an external reference is desired use the on-board
LTC6655-4.096 reference. It is enabled by stuffing 0Ω
resistors R7, R9 and R10 and removing 0Ω resistor R8.
Analog Input
The default driver for the analog inputs of the LTC2389-18
on the DC1826A is shown in Figure 2. This circuit converts
a single-ended 0V to 4.096V input signal applied at A
IN+
into a differential signal with a swing of ±4.096V between
the +IN and –IN inputs of the ADC. In addition, this circuit
band limits the input frequencies to approximately 16MHz.
It is also possible to drive the LTC2389-18 pseudo differ-
entially both with unipolar and bipolar outputs. The circuit
of Figure 3 shows the pseudo-differential unipolar driver.
This is connected on the DC1826A by removing R27 and
placing 0Ω resistors in the R31 and R42 positions.
Figure 4 shows the pseudo-differential bipolar driver circuit.
This is connected on the DC1826A by removing R29, R30,
C25 and C26 and placing 0Ω in the R30 position.
Alternatively, if your application circuit produces a differ-
ential signal which can drive the ADC, the circuit shown in
Figure 5 can be used. This is connected in the DC1826A
by removing R29, R30, R37, C23, C25 and C26 and by
adding a 0Ω resistor for R30 and R25. At this point it will
be necessary to drive both A
IN+
and A
IN–
.
Figure 2. Default Driver Circuit
Figure 4. Pseudo-Differential Bipolar Driver
Figure 3. Pseudo-Differential Unipolar Driver
Figure 5. Fully Differential Driver
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DEMO MANUAL DC1826A
DC1826A SETUP
AC-Coupling the Inputs
The circuit in Figure 5 can be AC-coupled on the DC1826A
by putting JP1 and JP2 in the AC position and adding a
1k resistor at the R11 and R40 locations. Using just JP1
and adding R11 allows a single-ended input signal to be
AC-coupled. AC-coupling the inputs may degrade the
distortion performance of the ADC due to nonlinearity of
the coupling capacitors (C12 and C31).
Data Collection
For SINAD, THD or SNR testing, a low noise, low distortion
generator such as the B&K Type 1051 or Stanford Research
DS360 should be used. A low jitter RF oscillator such as
the HP8644 or DC1216A-A is used as the clock source.
This demo board is tested in-house by attempting to du-
plicate the FFT plot shown in Figure 7a of the LTC2389-18
data sheet. This involves using a 2.5MHz clock source,
along with a sinusoidal generator at a frequency of 2kHz.
The input signal level is approximately –1dBfs. The input
is level shifted and filtered with the circuit shown in Fig-
ure 6. A typical FFT obtained with DC1826A is shown in
Figure 7. Note that to calculate the real SNR, the signal
level (F1 amplitude = –0.998dB) has to be added back to
the SNR that PScope displays. With the example shown in
Figure 7 this means that the actual SNR would be 98.50dB
instead of the 97.52dB that PScope displays. Taking the
RMS sum of the recalculated SNR and the THD yields a
SINAD of 98dB which is fairly close to the typical number
for this ADC.
There are a number of scenarios that can produce mis-
leading results when evaluating an ADC. One that is
common is feeding the converter with a frequency that
is a submultiple of the sample rate, and which will only
exercise a small subset of the possible output codes.
The proper method is to pick an M/N frequency for the
input sine wave frequency. N is the number of samples
in the FFT. M is a prime number between one and N/2.
Multiply M/N by the sample rate to obtain the input sine
wave frequency. Another scenario that can yield poor
results is if you do not have a signal generator capable of
ppm frequency accuracy or if it cannot be locked to the
clock frequency. You can use an FFT with windowing to
reduce the “leakage” or spreading of the fundamental, to
get a close approximation of the ADC performance. If an
amplifier or clock source with poor phase noise is used,
the windowing will not improve the SNR.
Layout
As with any high performance ADC, this part is sensitive
to layout. The area immediately surrounding the ADC on
the DC1826A should be used as a guideline for placement,
and routing of the various components associated with the
ADC. Here are some things to remember when laying out
a board for the LTC2389-18. A ground plane is necessary
to obtain maximum performance.
Keep bypass capacitors as close to supply pins as pos-
sible. Use individual low impedance returns for all bypass
capacitors. Use of a symmetrical layout around the analog
inputs will minimize the effects of parasitic elements. Shield
analog input traces with ground to minimize coupling from
other traces. Keep traces as short as possible.
Component Selection
When driving a low noise, low distortion ADC such as
the LTC2389-18, component selection is important so
as to not degrade performance. Resistors should have
low values to minimize noise and distortion. Metal film
resistors are recommended to reduce distortion caused
by self heating. Because of their low voltage coefficients,
to further reduce distortion NPO or silver mica capacitors
should be used. Any buffer used to drive the LTC2389-18
should have low distortion, low noise and a fast settling
time such as the LT6350.
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Figure 6. Level-Shift Circuit
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DEMO MANUAL DC1826A
DC1826A SETUP
Jumper and Switch Functions
JP1:
Selects AC- or DC-coupling of A
IN+
. The default setting
is DC.
JP2:
Selects AC- or DC-coupling of A
IN–
. The default setting
is DC.
JP3:
V
CM
sets the DC bias for A
IN+
and A
IN–
when the
inputs are AC-coupled. V
REF
/2 is the default setting.
JP4:
VCCIO sets the output levels at J2 to either 3.3V
or 2.5V. Use 3.3V to interface to the DC718 which is the
default setting.
JP5:
EEPROM default position is WP The position of this
.
jumper should not be changed.
SW1
SER_PARL:
Off enables serial operation. Sample rate is
the CLKIN frequency divided by 50. On enables parallel
operation. Sample rate is equal to the CLKIN frequency.
OB/2CL:
Off enables offset binary output code in fully-
differential mode and unipolar range with straight binary
code in pseudo-differential mode. On enables 2’s comple-
ment output code in fully-differential mode and bipolar
range with 2’s complement output code in pseudo-dif-
ferential mode.
CSL:
Off disables SDO and gates SCK off. On enables SDO
and gates SCK on.
PD/FDL:
Off enables pseudo-differential mode. On enables
fully-differential mode.
The default position for all switches is on.
Figure 7. PScope Screenshot
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