Mobile DiskOnChip P3
256Mb Flash Disk with
M-Systems’ x2 Technology
Preliminary Data Sheet, June 2003
Highlights
Mobile DiskOnChip™ P3, a member of
M-Systems’ DiskOnChip™ family of
optimized memory solutions for new-generation
mobile handsets, provides high performance
and reliability using NAND flash technology. It
combines Toshiba’s cutting-edge 0.13 micron
NAND flash manufacturing process enhanced
for performance and reliability with
M-Systems’ x2 technology.
Mobile DiskOnChip P3 optimizes real estate
and cost structure by incorporating the flash
array and an embedded thin controller in a
single die. A boot block can be used to boot the
OS or initialize the CPU/platform, replacing
expensive NOR flash and further reducing
memory system costs.
Mobile DiskOnChip P3 provides:
Flash disk for both code and data storage
Low voltage: 1.8V or 3.3 I/O (auto-detect),
3V Core
Hardware protection and security-enabling
features
High capacity: 256Mbit (32MByte)
Device cascading option: up to 1Gbit
(128MByte)
Enhanced Programmable Boot Block
enabling eXecute In Place (XIP)
functionality using 16-bit interface
Small form factors:
48-pin TSOP-I package
85-ball FBGA 7x10x1.2 mm package
Enhanced performance with:
Multi-plane operation
DMA support
MultiBurst operation
Turbo operation
Unrivaled data integrity with a robust Error
Detection Code/Error Correction Code
(EDC/ECC)
Maximized flash endurance with TrueFFS
®
6.1 (and higher) flash management software
Support for major mobile OSs, including:
Symbian OS, Pocket PC 2002/3,
Smartphone 2002/3, Palm OS, Nucleus,
Linux, Windows CE
Compatible with major mobile CPUs,
including TI OMAP, XScale, Motorola
DragonBall MX1 and Qualcomm
MSMxxxx.
1
Preliminary Data Sheet, Rev. 0.3
93-SR-009-8L
Mobile DiskOnChip P3
Performance
Boot Capability
MultiBurst read: 80 MB/sec
Sustained read: 5 MB/sec
Sustained write: 2.5 MB/sec
Access time:
Normal: 55 nsec
Turbo: 33 nsec
MultiBurst: 25 nsec
Protection & Security-Enabling Features
16-byte Unique Identification (UID)
number
6KByte user-controlled One Time
Programmable (OTP) area
Two configurable hardware-protected
partitions for data and code:
Read-only mode
Write-only mode
One-Time Write mode (ROM-like)
partition
Protection key and LOCK# signal
Sticky Lock (SLOCK) to lock boot
partition
Protected Bad Block Table
Reliability and Data Integrity
2KB Programmable Boot Block with XIP
capability to replace boot NOR
Download Engine (DE) for automatic
download of boot code from Programmable
Boot Block
Boot options:
CPU initialization
Platform initialization
OS boot
Asynchronous Boot mode to boot from
ARM-based CPUs, e.g. XScale, TI OMAP,
without the need for external glue logic
Exceptional boot performance with
MultiBurst operation and DMA support
enhanced by external clock
Hardware Compatibility
Hardware- and software-driven, on-the-fly
EDC and ECC algorithms
4-bit Error Detection Code/Error Correction
Code (EDC/ECC), based on a patented
combination of BCH and Hamming code
algorithms
Guaranteed data integrity after power
failure
Transparent bad-block management
Dynamic and static wear-leveling
Configurable interface: simple NOR-like or
multiplexed address/data interface
CPU compatibility, including:
ARM-based CPUs
Texas Instruments OMAP
Intel StrongARM/XScale
Motorola DragonBall MX1
Qualcomm MSMxxxx
AMD Alchemy
Motorola PowerPC™ MPC8xx
Philips PR31700
Hitachi SuperH™ SH-x
NEC VR Series
Supports 8-, 16- and 32-bit architectures
2
Data Sheet, Rev. 0.3
93-SR-009-8L
Mobile DiskOnChip P3
TrueFFS
®
Software
Full hard-disk read/write emulation for
transparent file system management
Patented TrueFFS
Flash file system management
Automatic block management
Data management to maximize the limit
of typical flash life expectancy
Dynamic virtual mapping
Dynamic and static wear-leveling
Programming, duplicating, testing and
debugging tools available in source code
Operating Environment
Power Requirements
Operating voltage
Core: 2.5V to 3.6V
I/O: 1.65 to 2.0V; or 2.5V to 3.6V
(auto-detect)
Current
Active: 10 mA
Deep Power-Down: 10
µA
Capacity and Packaging
Wide OS support, including:
Symbian OS (EPOC)
Pocket PC 2002/3
Smartphone 2002/3
Palm OS
Nucleus
Windows CE
Linux
TrueFFS Software Development Kit (SDK)
for quick and easy support for proprietary
OSs, or OS-less environment
TrueFFS Boot Software Development Kit
(BDK)
256Mb (32MB) capacity
Device cascading option for up to four
devices (1Gb)
48-pin TSOP-I package:
20x12x1.2 mm (width x length x height)
85-ball FBGA package:
7x10x1.2 mm (width x length x height)
Pinout compatible with DiskOnChip Plus
TSOP-I products
Ballout compatible with DiskOnChip Plus
69-ball FBGA products: 9x12x1.4 mm
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Data Sheet, Rev. 0.3
93-SR-009-8L
Mobile DiskOnChip P3
T
ABLE OF
C
ONTENTS
1. Introduction ............................................................................................................................... 5
2. Product Overview ...................................................................................................................... 6
2.1
2.2
Product Description ............................................................................................................ 6
Standard Interface .............................................................................................................. 7
2.2.1
2.2.2
2.2.3
Pin/Ball Diagrams................................................................................................................. 7
System Interface .................................................................................................................. 9
Signal Description .............................................................................................................. 10
Pin/Ball Diagram................................................................................................................. 14
System Interface ................................................................................................................ 16
Signal Description .............................................................................................................. 17
2.3
Multiplexed Interface ........................................................................................................ 14
2.3.1
2.3.2
2.3.3
3. Theory of Operation ................................................................................................................ 21
3.1
3.2
Overview........................................................................................................................... 21
System Interface............................................................................................................... 22
3.2.1
3.2.2
Standard (NOR-Like) Interface........................................................................................... 22
Multiplexed Interface .......................................................................................................... 22
3.3
3.4
Configuration Interface ..................................................................................................... 23
Protection and Security-Enabling Features ...................................................................... 23
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
Read/Write Protection ........................................................................................................ 23
Unique Identification (UID) Number ................................................................................... 23
One-Time Programmable (OTP) Area ............................................................................... 24
One-Time Write (ROM-Like) Partition ................................................................................ 24
Sticky Lock (SLOCK).......................................................................................................... 24
3.5
3.6
3.7
3.8
3.9
Programmable Boot Block with eXecute In Place (XIP) Functionality.............................. 24
Download Engine (DE) ..................................................................................................... 25
Error Detection Code/Error Correction Code (EDC/ECC) ................................................ 25
Data Pipeline .................................................................................................................... 25
Control and Status............................................................................................................ 25
3.10 Flash Architecture............................................................................................................. 26
4. x2 Technology ......................................................................................................................... 28
4.1
4.2
4.3
MultiBurst Operation......................................................................................................... 28
DMA Operation................................................................................................................. 30
Combined MultiBurst Mode and DMA Operation ............................................................. 31
1
Data Sheet, Rev. 0.3
93-SR-009-8L
Mobile DiskOnChip P3
4.4
5.1
5.2
6.1
6.2
6.3
7.1
Turbo Operation ............................................................................................................... 31
Method of Operation......................................................................................................... 32
Low-Level Structure of the Protected Area....................................................................... 33
Normal Mode .................................................................................................................... 36
Reset Mode ...................................................................................................................... 36
Deep Power-Down Mode ................................................................................................. 36
General Description.......................................................................................................... 38
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
Built-In Operating System Support..................................................................................... 39
TrueFFS Software Development Kit (SDK)........................................................................ 39
File Management................................................................................................................ 39
Bad Block Management ..................................................................................................... 39
Wear-Leveling .................................................................................................................... 39
Power Failure Management ............................................................................................... 40
Error Detection/Correction.................................................................................................. 40
Special Features Through I/O Control (IOCTL) Mechanism.............................................. 41
Compatibility ....................................................................................................................... 41
5. Hardware Protection ............................................................................................................... 32
6. Modes of Operation................................................................................................................. 35
7. TrueFFS Technology............................................................................................................... 38
7.2
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8KB Memory Window ....................................................................................................... 41
Definition of Terms ........................................................................................................... 42
Reset Values .................................................................................................................... 42
No Operation (NOP) Register........................................................................................... 43
Chip Identification (ID) Register [0:1]................................................................................ 43
Test Register .................................................................................................................... 43
Bus Lock Register ............................................................................................................ 44
Endian Control Register ................................................................................................... 45
DiskOnChip Control Register/Control Confirmation Register ........................................... 46
Device ID Select Register................................................................................................. 47
8. Register Descriptions ............................................................................................................. 42
8.10 Configuration Register...................................................................................................... 47
8.11 Interrupt Control Register ................................................................................................. 48
8.12 Interrupt Status Register................................................................................................... 49
8.13 Output Control Register.................................................................................................... 50
8.14 DPD Control Register ....................................................................................................... 51
2
Data Sheet, Rev. 0.3
93-SR-009-8L
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