• Lowest power FPGA with smallest package footprint
• Lowest power FPGA with high I/O-to-logic ratio
• Low power, high performance FPGA with up to
3 M system gates
• Low power, high performance FPGA with smallest pack-
age footprint
• Low power, high performance FPGA with Flash*Freeze
• Mixed signal FPGA
• Mixed signal integration down to –55ºC
• Reprogrammable digital logic, configurable analog,
embedded flash memory
• Unprecedented low power consumption across the
full military temperature range
• High-density fine-pitch ball grid packaging
• High Performance And Easy In-System Programming
• Industry’s first military screened flash FPGA
• Full processing to MIL-STD-883 Class B
• Established heritage on commercial and military aircraft
• I/O counts
4
IGLOO
®
2
SmartFusion
IGLOO/e
IGLOO nano
IGLOO PLUS
ProASIC
®
3/E
ProASIC3 nano
ProASIC3L
Fusion
5
6
7
8
9
10
11
12
13
Military SmartFusion, Fusion
and ProASIC3/EL
14
Military ProASIC
PLUS®
15
IGLOO and ProASIC Family
I/O Selector
FPGA Packages
Design Tools
Development Kits
Programmers
Intellectual Property Cores
16
• Package dimensions
• Design software for Microsemi FPGAs and SoC FPGAs
• Starter, evaluation and development kits
• FlashPro3 and Silicon Sculptor 3 programmers
• Microsemi Intellectual Property (IP) products designed
and optimized for use with Microsemi FPGAs
18
20
21
25
26
Please refer to www.microsemi.com/fpga-soc and appropriate product datasheets for the latest device information, valid ordering codes and more
information regarding previous generations of flash FPGAs.
www.microsemi.com/fpga-soc
3
SmartFusion2
The next-generation System-on-Chip FPGA
Microsemi’s next-generation SmartFusion2 System-on-Chip (SoC) FPGAs are the only devices that address fundamental requirements for advanced security,
high reliability and low power in critical industrial, military, aviation, communications and medical applications. SmartFusion2 integrates an inherently reliable
flash-based FPGA fabric, a 166 MHz ARM Cortex-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM and industry-required
high-performance communication interfaces all on a single chip.
SmartFusion2 Devices
SmartFusion2 Devices
Maximum Logic Elements
(4LUT + DFF)
1
Math Blocks (18x18)
Logic/DSP
Fabric Interface Controllers (FICs)
PLLs and CCCs
Security
Cortex-M3 + Instruction Cache
eNVM (K Bytes)
Microcontroller
Subsystem
(MSS)
eSRAM (K Bytes)
eSRAM (K Bytes) Non SECDED
CAN, 10/100/1000 Ethernet,
HS USB
Multi-Mode UART, SPI, I
2
C, Timer
LSRAM 18 K Blocks
Fabric Memory
uSRAM 1 K Blocks
Total RAM (K bits)
DDR Controllers (count x width)
High Speed
SERDES Lanes (T)
PCIe End Points
MSIO (3.3 V)
Sm a rtF u si on2
User I/O
MSIOD (2.5 V)
DDRIO (2.5 V)
Total User I/O
0
0
115
28
66
209
123
40
70
233
10
11
191
21
22
400
1x18
4
1
157
40
70
267
139
62
176
377
31
34
592
128
256
64
80
1 each
2 each
69
72
1314
2x36
8
109
112
2074
1x18
4
2
309
40
76
425
292
106
176
574
8
160
160
3040
2x36
16
4
292
106
176
574
236
240
4488
2
AES256, SHA256, RNG
Yes
512
M2S005
6,060
11
M2S010
12,084
22
1
6
M2S025
27,696
34
M2S050
56,340
72
M2S090
86,316
84
2
8
AES256, SHA256, RNG, ECC, PUF
M2S100
99,512
160
M2S150
146,124
240
Notes:
1. Total logic may vary based on utilization of DSP and memories in your design. Please see the SmartFusion2 Fabric UG for details.
The FPGA with high level of integration at the lowest total system cost
The IGLOO2 FPGA family provides a 4-input look-up table (LUT) based fabric, 5G transceivers, high-speed general purpose I/O (GPIO), block RAM and
digital signal processing (DSP) blocks in a differentiated, cost- and power-optimized architecture. This next-generation IGLOO2 FPGA architecture offers up to
5x more logic density and 3x more fabric performance than its predecessors and combines a non-volatile flash-based fabric with the highest number of GPIO,
5G serialization/deserialization (SERDES) interfaces and PCI Express
®
(PCIe
®
) endpoints when compared to other products in its class.
• Highest number of 5G
transceivers
1
• Highest number of GPIO
1
• Highest number of PCI
compliant 3.3 V I/O
1
• Only FPGA with hardened
memory subsystem
• Only non-volatile and instant-on
mainstream FPGA
• 10x lower static power with
the same performance
• 1 mW in Flash*Freeze mode
• Only FPGA with SEU immune
fabric and mainstream features
• Extended temperature support
(up to 125ºC Tj)
• Built-in state-of-the-art design
security for all devices
• Root-of-trust
• Easy-to-use
IGLOO2 Devices
Features
Maximum Logic Elements
(4LUT + DFF)
1
Math Blocks (18x18)
Logic/DSP
PLLs and CCCs
SPI/HPDMA/PDMA
Fabric Interface Controllers (FICs)
Security
eNVM (K Bytes)
LSRAM 18 K Blocks
Memory
uSRAM 1 K Blocks
eSRAM (K Bytes)
Total RAM (K bits)
DDR Controllers
High Speed
SERDES Lanes (T)
PCIe End Points
MSIO (3.3 V)
User I/Os
MSIOD (2.5 V)
DDRIO (2.5 V)
Total User I/O
0
0
115
28
66
209
123
40
70
233
703
912
1x18
4
1
157
40
70
267
139
62
176
377
1104
128
10
11
21
22
1
AES256, SHA256, RNG
256
31
34
69
72
64
1826
2x36
8
2586
1x18
4
2
309
40
76
425
292
106
176
574
8
3552
2x36
16
4
292
106
176
574
IGL OO 2
5000
109
112
M2GL005
6,060
11
2
M2GL010
12,084
22
M2GL025
27,696
34
M2GL050
56,340
72
6
1 each
2
AES256, SHA256, RNG, ECC, PUF
512
160
160
236
240
M2GL090
86,316
84
M2GL100
99,512
160
8
M2GL150
146,124
240
Note:
1. Total logic may vary based on utilization of DSP and memories in your design. Please see the IGLOO2 Fabric UG for details.
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