Philips Semiconductors
Product data
18-bit to 36-bit address driver with bus hold (3-State)
74ALVCHS16830
FEATURES
•
Diodes on inputs clamp overshoot
•
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V HBM per method A114.
PIN CONFIGURATION
TOP VIEW
2Y2
1Y2
GND
2Y1
1Y1
V
CC
A1
A2
GND
1
2
3
4
5
6
7
8
9
80 1Y3
79 2Y3
78 GND
77 1Y4
76 2Y4
75 V
CC
74 1Y5
73 2Y5
72 GND
71 1Y6
70 2Y6
69 GND
68 1Y7
67 2Y7
66 V
CC
65 1Y8
64 2Y8
63 GND
62 1Y9
61 2Y9
60 1Y10
59 2Y10
58 GND
57 1Y11
56 2Y11
55 V
CC
54 1Y12
53 2Y12
52
GND
51 1Y13
50 2Y13
49 GND
48 1Y14
47 2Y14
46 V
CC
45 1Y15
44 2Y15
43 GND
42 1Y16
41 2Y16
•
Latch-up testing is done to JEDEC Standard JESD78, which
exceeds 100 mA.
•
Bus hold on data inputs eliminates the need for external
pullup/pulldown resistors
•
Packaged in thin very small-outline package (TVSOP) — 0.4 mm
pitch
•
Optimized for use with PCK953 in SDRAM module applications
•
Low noise, low skew
DESCRIPTION
The ALVCHS16830 address driver is designed for 2.3 V to 3.6 V
V
CC
operation.
Diodes to V
CC
have been added on the inputs to clamp overshoot.
The bus hold feature retains the inputs’ last state whenever the input
bus goes to high impedance. This prevents floating inputs and
eliminates the need for pull up or pull down resistors.
To ensure the high-impedance state during power up or power
down, the output-enable (OE) input should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is determined by
the current-sinking capability of the driver.
The 74ALVCHS16830 is characterized for operation from –40 to
+85
°C.
A3 10
A4 11
GND 12
A5 13
A6 14
V
CC
15
A7 16
A8 17
GND 18
A9 19
OE1 20
OE2 21
A10 22
GND 23
A11 24
FUNCTION TABLE
Inputs
OE1
L
L
H
H
L
L
H
OE2
H
H
L
L
L
L
H
A
H
L
H
L
H
L
X
H
L
Z
Z
H
L
Z
Outputs
1Yn
2Yn
Z
Z
H
L
H
L
Z
A12 25
V
CC
26
A13 27
A14 28
GND 29
A15 30
A16 31
GND 32
A17 33
A18 34
V
CC
35
2Y18 36
1Y18 37
GND 38
2Y17 39
1Y17 40
SW00723
ORDERING INFORMATION
PACKAGES
80-pin plastic thin very small outline (TVSOP)
TEMPERATURE RANGE
–40 to +85
°C
ORDER CODE
74ALVCHS16830DGB
DWG NUMBER
SOT647-1
2002 Mar 15
2
853-2280 27859
Philips Semiconductors
Product data
18-bit to 36-bit address driver with bus hold (3-State)
74ALVCHS16830
LOGIC DIAGRAM (POSITIVE LOGIC)
V
CC
PIN DESCRIPTION
PIN(S)
6, 15, 26, 35, 46, 55, 66, 75
7, 8, 10, 11, 13, 14, 16, 17, 19,
22, 24, 25, 27, 28, 30, 31, 33, 34
SYMBOL
V
CC
An
1Yn, 2Yn
FUNCTION
Supply voltage
Inputs
Outputs
OE2
21
V
CC
OE1
20
V
CC
5 1Y1
1, 2, 4, 5, 36, 37, 39, 40, 41, 42,
44, 45, 47, 48, 50, 51, 53, 54,
56, 57, 59, 60, 61, 62, 64, 65,
67, 68, 70, 71, 73, 74, 76, 77,
79, 80
20, 21
3, 9, 12, 18, 23, 29, 32, 38, 43,
49, 52, 58, 63, 69, 72, 78
OE1, OE2
GND
Output enable
Ground
A1
7
4
2Y1
to 17 other channels
SW00724
ABSOLUTE MAXIMUM RATINGS
Over recommended operating free-air temperature range (unless otherwise noted).
1
SYMBOL
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
, I
GND
Θ
JA
T
stg
PARAMETER
Supply voltage range
Input voltage range
Output voltage range
Input clamp current
Output clamp current
Continuous output current
Continuous current through each V
CC
or GND
Package thermal impedance
Storage temperature range
See Note 4
See Note 2
See Notes 2 and 3
V
I
< 0
V
O
< 0
CONDITIONS
RATING
–0.5 to +4.6
–0.5 to +4.6
–0.5 to V
CC
+0.5
–50
–50
"50
"100
106
–65 to +150
UNIT
V
V
V
mA
mA
mA
mA
°C/W
°C
NOTES:
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The package thermal impedance is calculated in accordance with JESD 51.
2002 Mar 15
3
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