Si8900/1/2
I
SOLA TED
M
ONITORING
ADC
Features
ADC
input channels
10-bit resolution
2 µs conversion time
3
Isolated serial I/O port
UART
I
(Si8900)
C/SMbus (Si8901)
2.5 MHz SPI port (Si8902)
2
Transient immunity:
45 kV/µs (typ)
Temperature range:
–40 to +85 °C
>60-year life at rated working
voltage
CSA component notice 5A
approval
IEC 60950, 61010, 60601
VDE/IEC 60747-5-2
UL1577 recognized
Up
to 5 kVrms for 1 minute
Ordering Information:
See page 25.
Applications
Isolated data acquisition
AC mains monitor
Solar inverters
Isolated temp/humidity sensing
Switch mode power systems
Telemetry
Pin Assignments
VDDA
VREF
AIN0
AIN1
VDDB
NC
NC
Rx
Tx
NC
VDDB
GNDB
VDDB
NC
NC
SCL
SDA
NC
VDDB
GNDB
Description
The Si8900/1/2 series of isolated monitoring ADCs are useful as linear
signal galvanic isolators, level shifters, and/or ground loop eliminators in
many applications including power-delivery systems and solar inverters.
These devices integrate a 10-bit SAR ADC subsystem, supervisory state
machine and isolated UART (Si8900), I
2
C/SMbus port (Si8901), or SPI
Port (Si8902) in a single package. Based on Silicon Labs’ proprietary
CMOS isolation technology, ordering options include a choice of 2.5 or
5 kV isolation ratings. All products are safety certified by UL, CSA, and
VDE. The Si8900/1/2 devices offer a typical common-mode transient
immunity performance of 45 kV/µs for robust performance in noisy and
high-voltage environments. Devices in this family are available in 16-pin
SOIC wide-body packages.
AIN2
NC
RST
GNDA
VDDA
VREF
AIN0
AIN1
AIN2
RST
RSDA
Si8900
Si8901
Safety Approval
GNDA
UL 1577 recognized
to 5
Up
kVrms for 1 minute
VDE certification conformity
IED 60747-5-2 (VDE 0884 Part 2)
VDDA
RST
NC
VREF
AIN0
AIN1
AIN2
GNDA
VDDB
NC
SDO
SCLK
SDI
EN
VDDB
GNDB
CSA component notice 5A
approval
IEC
60950, 61010, 60601
Si8902
Rev. 1.1 10/12
Copyright © 2012 by Silicon Laboratories
Si8900/1/2
Si8900/1/2
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. ADC Data Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1. UART (Si8900) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2. I
2
C/SMBus (Si8901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3. SPI Port (Si8902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4. Master Controller Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Si8900/1/2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1. Isolated Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.2. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.3. Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7. Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
11.1. Si8900/1/2 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Rev. 1.1
3
Si8900/1/2
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Input Side Supply Voltage
Input Side Supply Current
Symbol
V
DDA
I
DDA
Condition
With respect to GND1
V
DDA
= 3.3 V, Si890x active
V
DDA
= 3.3 V, Si890x idle
Output Side Supply Voltage
Output Side Supply Current
V
DDB
I
DDB
With respect to GND2
V
DDB
= 3.3 V to 5.5 V, Si890x active
V
DDB
= 3.3 V to 5.5 V, Si890x idle
Operating Temperature
T
A
Min
2.7
—
—
2.7
—
—
–40
Typ
—
10
8.6
—
4.4
3.3
—
Max
3.6
13.3
11.4
5.5
5.8
3.9
+85
°C
V
mA
Unit
V
mA
Table 2. Electrical Specifications
Parameter
ADC
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Full Scale Error
Offset Tempco
Input Voltage Range
Sampling Capacitance
Input MUX Impedance
Power Supply
Rejection
Reference Voltage
VREF Supply Current
ADC Conversion Time
R
INL
DNL
OFS
FSE
T
OS
V
IN
C
IN
R
MUX
PSRR
V
REF
I
VREF
t
CONV
Default V
REF
= V
DDA
VREF = 2.4 V
VREF = 2.4 V,
Guaranteed Monotonic
—
—
–2
–2
—
0
—
—
—
0
—
5
5
–70
—
12
2
10
±0.5
±0.5
0
0
45
±1
±1
+2
+2
—
V
REF
—
—
—
V
DDA
—
bits
LSB
LSB
LSB
LSB
ppm/°C
V
pF
k
dB
V
µA
µs
Symbol
Test Condition
Min
Typ
Max
Unit
4
Rev. 1.1
Si8900/1/2
Table 2. Electrical Specifications (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reset and Undervoltage Lockout
Power-on RESET
Voltage Threshold High
Power-on RESET
Voltage Threshold Low
VDDA Power-On Reset Ramp
Time
Power-On Reset
Delay Time
Output Side UVLO Threshold
Output side UVLO
Hysteresis
Digital Inputs
Logic High Level Input Voltage
Logic Low Level Input Voltage
Logic Input Current
Input Capacitance
Digital Outputs
Logic High Level Output Voltage
V
OH
V
DDB
= 5 V,
I
OH
= –4 mA
V
DDB
= 3.3 V,
I
OH
= –4 mA
Logic Low Level Output Voltage
Digital Output Series Impedance
Serial Ports
UART Bit Rate
SMBus/I
2
C Bit Rate
SPI Port
Slave
Address = 1111000x
60
—
—
—
—
—
234
240
2.5
kbps
kbps
Mbps
V
OL
R
OUT
V
DDB
= 3.3 to 5 V,
I
OL
= 4 mA
V
DDB
–0.4
3.1
—
—
4.8
—
0.2
85
—
—
0.4
—
V
V
V
V
IH
V
IL
I
IN
C
IN
VIN = 0 V or V
DD
0.7 x V
DDB
—
–10
—
15
—
—
—
0.6
+10
—
V
V
µA
pF
VRSTH
VRSTL
tRAMP
tPOR
UVLO
H
Time from VDDA = 0 V
to VDDA > VRST
tRAMP < 1 ms
—
—
2.3
100
—
1.7
—
—
—
—
1.8
—
1
0.3
—
—
V
V
ms
ms
V
mV
Rev. 1.1
5
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