G -LINK
GLT4160L16
1M X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Mar 2004 (Rev.4.3)
Features :
∗
∗
∗
∗
∗
1,048,576
words by 16 bits organization.
Fast access time and cycle time.
Dual
CAS
Input.
Low power dissipation.
Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden
Description :
The GLT4160L16 is a 1,048,576 x 16 bit
high-performance CMOS dynamic random
access memory. The GLT4160L16 offers
Fast Page mode with Extended Data Output,
and has both BYTE WRITE and WORD
WRITE access cycles via two
CAS
pins. The
GLT4160L16 has symmetric address and
accepts 1024-cycle refresh in 16ms interval.
All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 1024 x 16 bits within a page, with cycle
times as short as 18ns.
The GLT4160L16 is best suited for
graphics, and DSP applications requiring high
performance memories.
∗
∗
∗
∗
∗
∗
∗
Refresh and Test Mode Capability.
1024 refresh cycles per 16ms.
Available in 400 mil SOJ / TSOPII
Packages.
Single 3.3V±0.3V Power Supply.
All inputs and Outputs are TTL
compatible.
Extended Data-Out(EDO) Page Mode
operation.
Self – refresh capability. (S-Version).
Extended Temperature Available
( -25°C ~ 85°C )
HIGH PERFORMANCE
Max.
RAS
Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
Max.
CAS
Access Time (t
CAC
)
45
50
50 ns
25 ns
20 ns
85 ns
14 ns
60
60 ns
30 ns
25 ns
104 ns
15 ns
70
70 ns
35 ns
30 ns
124 ns
20 ns
45 ns
22 ns
18 ns
80 ns
12 ns
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw
Email : sales@glink.com.tw
TEL : 886-2-27968078
-1-
G -LINK
Pin Configuration :
GLT416016
SOJ Top View
Vcc
DQ
0
DQ
1
DQ
2
DQ
3
Vcc
DQ
4
DQ
5
DQ
6
DQ
7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
DQ
11
DQ
10
DQ
9
DQ
8
NC
LCAS
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Vcc
DQ
0
DQ
1
DQ
2
DQ
3
Vcc
DQ
4
DQ
5
DQ
6
DQ
7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GLT4160L16
1M X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Mar 2004 (Rev.4.3)
TSOP(Type II)
Top View
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
DQ
11
DQ
10
DQ
9
DQ
8
NC
NC
LCAS
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Descriptions:
Name
A
0
- A
9
RAS
UCAS
LCAS
WE
OE
Function
Address Inputs
Row Address Strobe
Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable
Data Inputs / Outputs
+3.3V Power Supply
Ground
No Connection
DQ
0
- DQ
15
V
CC
V
SS
NC
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw
Email : sales@glink.com.tw
TEL : 886-2-27968078
-2-
G -LINK
Absolute Maximum Ratings*
Operating Temperature, T
A
(ambient)
.....................................…0°C to +70°C
……….………………(extended)..–25°C to +85°C
Storage Temperature(plastic).….-55°C to +150°C
Voltage Relative to V
SS
..........…...-1.0V to + 4.6V
Short Circuit Output Current.…...................50mA
Power Dissipation........…............................1.0W
*Note:Operation above Absolute Maximum Ratings can
abversely affect device reliability.
GLT4160L16
1M X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Mar 2004 (Rev.4.3)
Capacitance*
T
A
=25°C, V
CC
=3.3V±0.3V, V
SS
=0V
Symbol Parameter
C
IN1
C
IN2
C
OUT
Address Input
RAS
,
LCAS
,
UCAS
,
WE
,
OE
Max.
5
7
7
Unit
pF
pF
pF
Data Input/Output
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
CAS
means
UCAS
and
LCAS
.
All voltages are referenced to GND.
After power up, wait more than 100µs and then, execute eight
CAS
-before-
RAS
or
RAS
-only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
RAS
LCAS
UCAS
WE
Clock
Generator
Upper
Byte
Control
Lower
Byte
Control
X8
OE
Data
Output
Buffer
X8
DQ0
|
DQ7
Row Decoder
CAS before
RAS Counter
Memory
Array
1024X1024X16
X8
Vcc
GND
Data
Input
Buffer
...1024...
X8
...1024X16...
X8
Data
Output
Buffer
X8
Sense Amplifier
Row
Address
Buffer
Column
Address
Buffer
Y0..Y9
X1
6
DQ8
|
DQ15
Data
Input
Buffer
A0
|
A9
X0..X9
....1024....
X8
X8
Column Decoder
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw
Email : sales@glink.com.tw
TEL : 886-2-27968078
-3-
G -LINK
Truth Table: GLT4160L16
Function
Stanby
Read: Word
Read: Lower Byte
Read: Upper Byte
Write: Word(Early Write)
Write: Lower Byte
(Early)
Write: Upper Byte
(Early)
Read Write
EDO-Page- 1st Cycle
Mode Read 2nd Cycle
EDO-Page- 1st Cycle
Mode Write 2nd Cycle
EDO-Page- 1st Cycle
Mode Read-
Write
Hidden
Refresh
2nd Cycle
Read
Write
RAS
-Only Refresh
GLT4160L16
1M X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Mar 2004 (Rev.4.3)
RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
CASL
H
L
L
H
L
L
H
L
H→L
H→L
H→L
H→L
H→L
CASH
H
L
H
L
L
H
L
L
H→L
H→L
H→L
H→L
H→L
WE
X
H
H
H
L
L
L
H→L
H
H
L
L
H→L
OE
X
L
L
L
X
X
X
L→H
L
L
X
X
L→H
ADDRESS
High-Z
DQs
Notes
ROW/COL Data Out
ROW/COL Lower Byte,Data-Out
Upper Byte,High-Z
ROW/COL Lower Byte,High-Z
Upper Byte,Data-Out
ROW/COL Data-In
ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
ROW/COL Data-Out,Data-In
ROW/COL Data-Out
COL
Data-Out
1,2
2
2
2
2
1,2
ROW/COL Data-In
COL
Data-In
ROW/COL Data-Out,Data-In
L
L→H→L
L→H→L
L
H→L
H→L
L
L
H
L
H→L
L
L
H
L
H→L
H
H
X
X
L→H
L
L
X
X
COL
Data-Out,Data-In
1,2
2
2
ROW/COL Data-Out
ROW/COL Data-In
ROW
High-Z
High-Z
CBR Refresh
3
Notes:
1. These READ cycles may also be BYTE READ cycles (either
UCAS
or
LCAS
active).
2. These WRITE cycles may also be BYTE WRITE cycles (either
UCAS
or
LCAS
active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (
UCAS
or
LCAS
).
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw
Email : sales@glink.com.tw
TEL : 886-2-27968078
-4-
G -LINK
DC and Operating Characteristics (1-2)
GLT4160L16
1M X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Mar 2004 (Rev.4.3)
T
A
= 0°C to 70°C,-25°C to 85°C (extended temperature) V
CC
=3.3V±0.3V, V
SS
=0V, unless otherwise specified.
Sym.
I
LI
I
LO
I
CC1
Parameter
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
Operating Current,
Random READ/WRITE
Test Conditions
0V
≤
V
IN
≤
Vcc+0.3V
(All other pins not under test=0V)
0V
≤
V
out
≤
Vcc
Output is disabled (Hiz)
t
RC
= t
RC
(min.)
Access
Time
Min. Typ Max. Unit Notes
-5
-5
+5
+5
150
150
140
130
1
µA
µA
t
RAC
= 45ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
mA
1,2
I
CC2
I
CC3
Standby Current,(TTL)
RAS , UCAS , LCAS at V
IH
other inputs
≥V
SS
RAS cycling, UCAS , LCAS at V
IH
t
RC
= t
RC
(min.)
t
RAC
= 45ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
t
RAC
= 45ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
t
RAC
= 45ns
t
RAC
= 50ns
t
RAC
= 60ns
t
RAC
= 70ns
mA
Refresh Current,
RAS -Only
I
CC4
Operating Current,
EDO Page Mode
RAS at V
IL
, UCAS , LCAS address
cycling:t
PC
=t
PC
(min.)
I
CC5
Refresh Current,
CAS Before RAS
RAS , UCAS , LCAS
address cycling:
t
RC
=t
RC
(min.)
RAS
≥V
CC
-0.2V,
UCAS
≥V
CC
-0.2V,
LCAS
≥V
CC
-0.2V,
All other inputs V
SS
150
150
140
130
150
150
140
130
150
150
140
130
mA
2
mA
1,2
mA
1
I
CC6
Standby Current,
(CMOS)
300
µA
1,5
I
CC7
Self Refresh Current
RAS = UCAS = LCAS =V
IL
WE = OE =A
0
~A
9
=V
CC
-0.2V or 0.2V
DQ
0
~DQ
15
=V
CC
-0.2V,0.2V or Open
300
-0.3
2.0
I
OL
= 2mA
I
OH
= -2mA
2.4
+0.8
V
CC
+0.3
0.4
µA
V
V
V
V
3
3
V
IL
V
IH
V
OL
V
OH
Notes:
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1.I
CC
is dependent on output loading when the device output is selected. Specified I
CC
(max.) is measured with the output open.
2.I
CC
is dependent upon the number of address transitions specified I
CC
(max.) is measured with a maximum of one transition per address
cycle in random Read/Write and EDO Fast Page Mode.
3.Specified V
IL
(min.) is steady state operation. During transitions V
IL
(min.) may undershoot to -1.0V for a period not to exceed 15ns. All AC
parameters are measured with V
IL
(min.)≥V
SS
and V
IH
(max.)≤V
CC
.
4.Specified V
IH
(max.) is steady state operation. During transitions V
IH
(max.) may undershoot to +1.0V for a period not to exceed 15ns. All AC
parameters are measured with V
IL
(min.)≥V
SS
and V
IH
(max.)≤V
CC
.
5.S-Version.
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw
Email : sales@glink.com.tw
TEL : 886-2-27968078
-5-
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
