DEMO MANUAL DC1946A
LTC6430 and LTC2158
15dB Differential Amplifier
and 14-Bit, 310Msps Dual ADC
Description
Demonstration circuit 1946A supports the
LTC
®
6430
and
the
LTC2158
high speed ADC. It was specially designed
for applications that include an LTC6430, a high speed
amplifier with 15dB of gain.
The circuitry on the analog inputs is optimized for analog
input frequencies from 50MHz up to 1GHz. Refer to the
Table 1. DC1946A
DEMONSTRATION
CIRCUIT
1946A
ADC PART NUMBER
LTC2158-14
AMPLIFIER PART
NUMBER
LTC6430-15
RESOLUTION
14-BIT
MAXIMUM SAMPLE
RATE
310Msps
INPUT FREQUENCY
50-1000MHz
data sheet for proper input networks for different input
frequencies
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
Table 2. Performance Summary (T
A
= 25°C)
PARAMETER
Supply Voltage – ADC (V
+
)
Supply Voltage – Amplifier (+5V)
Analog Input Range
Logic Input Voltages
Logic Output Voltages (Differential)
Minimum Logic High
Maximum Logic Low
Nominal Logic Levels (100Ω Load, 3.5mA Mode,
1.25V Common Mode)
Minimum Logic levels (100Ω Load, 3.5mA Mode,
1.25V Common Mode)
Sampling Frequency (Encode Clock Frequency)
Encode Clock Level (Single-Ended at J2)
Encode Clock Level (Differential at J2)
Minimum Logic Levels (ENC
–
Tied to GND)
Maximum Logic Level (ENC
–
Tied to GND)
Minimum Logic Levels (ENC
–
Not Tied to GND,
1.2V Common Mode)
0.2
10
0
3.6
350
247
310
1.2
0.6
CONDITION
This Supply Must Provide Up to 800mA.
This Supply Must Provide Up to 500mA.
This Pin Is Unregulated
MIN
3.0
4.75
5
TYP
MAX
6
5.25
400
UNIT
V
V
mV
P-P
V
V
mV
mV
MHz
V
V
V
dc1946af
1
DEMO MANUAL DC1946A
Quick start proceDure
Demonstration circuit 1946A is easy to set up to evaluate
the performance of the LTC2158 A/D converter. Refer to
Figure 1 for proper measurement equipment setup and
follow the procedure below:
SETUP
The DC1371 USB demonstration circuit was supplied
with the DC1946A global demonstration circuit, follow the
DC1371 Quick Start Guide to install the required software
and for connecting the DC1371 to the DC1946A and to a PC.
3.0V TO 5V
JUMPERS SHOWN IN
THEIR DEFAULT POSITIONS
DIFFERENTIAL
ANALOG INPUTS
CHANNEL 1
+5V
CHANNEL 2
THE DC1946 CONNECTS
TO THE DC1371 VIA AN
FMC CONNECTOR
SINGLE-ENDED
ENCODE CLOCK
Figure 1. DC1946A Setup (Zoom for Detail)
2
dc1946af
DEMO MANUAL DC1946A
Quick start proceDure
hARDwARE SETUP
SMAs
J4 & J5:
Channel 1 Analog Inputs: As a default the
DC1946A is populated to accept a single-ended input. Ap-
ply a single-ended signal to J4. For use with a differential
signal remove R3 and populate R11 with a 0Ω resistor.
Apply a differential signal to these SMA connectors from
a differential driver. These SMAs are positioned 0.8" apart
to accommodate LTC differential driver boards.
J6 & J7:
Channel 2 Analog Inputs. As a default the
DC1946A is populated to accept a single-ended input. Ap-
ply a single-ended signal to J6. For use with a differential
signal remove R7 and populate R13 with a 0Ω resistor.
Apply a differential signal to these SMA connectors from
a differential driver. These SMAs are positioned 0.8" apart
to accommodate LTC differential driver boards.
J2 CLK+:
Positive Encode Clock Input. As a default the
demo board is populated to accept a single-ended clock
input from a low jitter signal generator. For other popula-
tion options see the encode clock section of this manual.
J3 CLK–:
Negative Encode Clock Input. As a default this
input port is grounded to accommodate the single-ended
clock drive. For other population options see the encode
clock section of this manual.
Turrets
V+ :
Positive input voltage for the ADC and digital buffers.
This voltage feeds a regulator that supplies the proper
voltages for the ADC and buffers. The voltage range for
this turret is 3.3V to 5V.
+5V:
Positive input voltage for the LTC6430. Apply a 5V
signal to this turret to power the LTC6430. This turret is
connected to the amplifier directly and is not regulated.
There is a resistor on the back of the board R14 that will
connect the power pins of the two amplifiers. By removing
this resistor each amplifier can be powered independently.
SENSE:
Optional Reference Voltage. This pin is connected
directly to the SENSE pin of the ADC. Connect SENSE to a
1.25V external reference and the external reference mode
is automatically selected. The external reference must be
1.25V ±25mV for proper operation. If no external voltage
is supplied, this pin will be pulled up to V
DD
through a
weak pull-up resistor.
GND:
Ground Connection. This demo board only has a
single ground plane. This turret should be tied to the GND
terminal of the power supply being used.
Jumpers
The DC1946A demonstration circuit should have the fol-
lowing jumper settings as default positions (per Figure 1)
which configure the ADC in serial programming mode.
In the default configuration JP1-JP2 should be left in the
default locations. This will pull PAR/SER low putting the
part in serial configuration mode.
JP1-PAR/SER:
Selects Parallel or Serial Programming
Mode (Default: Serial). The DC1946A will not work in parallel
programming mode unless a custom FPGA load is used.
JP2-EEPROM:
EEPROM Write Protect. For factory use
only. Should be left in the enable (PROG) position.
APPLYING POwER AND SIGNALS TO ThE DC1946A
DEMONSTRATION CIRCUIT
If a DC1371 is used to acquire data from the DC1946A,
the DC1371 must FIRST be connected to a powered USB
port and provided an external 5V BEFORE applying +3V to
+5.0V across the pins marked V+ and GND on the DC1946A.
The 5V for the LTC6430 should be applied after the ADC
is powered. DC1946A requires 3V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The power for the LTC6430 is unregulated. The
DC1946A demonstration circuit requires up to 800mA on
V+ and 500mA on +5V. The DC1946A should not be re-
moved or connected to the DC1371 while power is applied.
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3
DEMO MANUAL DC1946A
Quick start proceDure
ANALOG INPUT NETwORK
The input network of the DC1946A can be modified to ac-
commodate various applications. In the default setup J4 and
J6 are used as single-ended inputs. Onboard transformers
are used to do a single-ended-to-differential translation
to drive the LTC6430 differentially. If differential drive is
desired both of the inputs are brought out to SMA connec-
tors so the demo board can be driven with a differential
source. To drive the demo board with a differential source
simply remove R3 and R7 and populate R11 and R13 with
0Ω resistors. Then remove T1 and T2 and jump over the
pads with 0Ω resistors. This will allow the board to be
driven differentially from a differential source. The inputs
SMA connectors for the input signals are 0.8" apart to
accommodate LTC differential driver boards.
In almost all cases, off board filters will be required on
the analog input of the differential driver to produce data
sheet SNR.
The off board filters should be located close to the inputs of
the differential driver to avoid reflections from impedance
discontinuities at the driven end of a long transmission line.
Most filters do not present 50Ω outside the passband. In
some cases, 3dB to 10dB pads may be required to obtain
low distortion.
Apply the analog input signal of interest to the SMA con-
nectors on the DC1946A marked J4 and J6.
ENCODE CLOCK
Apply an encode clock to the SMA connector on the
DC1946A demonstration circuit board marked J2. As a
default the DC1946A is populated to have a single-ended
clock input. It is possible to modify the demo board.
For the best noise performance, the encode input must be
driven with a very low jitter signal source. The amplitude
should be as large as possible up to 2V
P-P
or 10dBm.
Using bandpass filters on the clock and the analog input will
improve the noise performance by reducing the wideband
noise power of the signals. In the case of the DC1946A, a
bandpass filter used for the clock should be used prior to
the DC1075A. Data sheet FFT plots are taken with 10-pole
LC filters made by TTE (Los Angeles, CA) to suppress signal
generator harmonics, nonharmonically related spurs and
broadband noise. Low phase noise Agilent 8644B genera-
tors are used with TTE bandpass filters for both the clock
input and the analog input.
When using a PECL or LVDS clock you can drive the
DC1946A differentially through J2 and J3. From the default
population, remove the resistors in the R33, R22 and R23
positions and populate 0Ω resistors in the R31, R32, R34,
and R35 positions. Add the appropriate termination for
your clock signal. R27, R28, R29, R30 and R26 are avail-
able to provide the proper termination for LVDS, PECL,
or CML signaling. Blocking capacitors can be installed in
the R44 and R45 positions if the common mode voltage
of the clock is not compatible with the LTC2158.
SOFTwARE
The DC1371 is controlled by the PScope™ system soft-
ware provided or downloaded from the Linear Technology
website at http://www.linear.com/software/. If a DC1371
was provided, follow the DC1371 Quick Start Guide and
the instructions below.
To start the data collection software if “PScope.exe”, is
installed (by default) in \Program Files\LTC\PScope\, double
click the PScope icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC1946A demonstration circuit is properly connected
to the DC1371, PScope should automatically detect the
DC1946A, and configure itself accordingly. If necessary
the procedure below explains how to manually configure
PScope.
Under the “Configure” menu, go to “ADC Configuration....”
Check the “Config Manually” box and use the following
configuration options, see Figure 2:
Manual Configuration settings:
Bits: 14
Alignment: 16
FPGA Ld: S2157
Channs: 2
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4
DEMO MANUAL DC1946A
Quick start proceDure
Figure 2: ADC Configuration
Bipolar: Unchecked
Positive-Edge Clk: Unchecked
If everything is hooked up properly, powered and a suit-
able encode clock is present, clicking the “Collect” button
should result in time and frequency plots displayed in
the PScope window. Additional information and help for
PScope is available in the DC1371 Quick Start Guide and in
the online help available within the PScope program itself.
SERIAL PROGRAMMING
PScope has the ability to program the DC1946A board
serially through the DC1371. There are several options
available for the LTC2158 that are only available through
serially programming. PScope allows all of these features
to be tested.
These options are available by first clicking on the “Set
Demo Bd Options” icon on the PScope toolbar (Figure 3).
Figure 4: Demobd Configuration Options
Sleep Mode –
Selects between normal operation, sleep
modes:
Off (Default): ADC is powered and active
On: ADC is powered down
Nap Mode –
ADC core powers down while references
stay active:
Figure 3: PScope Toolbar
Off (Default): ADC is powered and active
On: ADC is put into nap mode
Power Down B –
Powers down channel 2 while references
stay active:
Off (Default): ADC is powered and active
On: Channel 2 of ADC is powered down
dc1946af
This will bring up the menu shown in Figure 4.
This menu allows any of the options available for the
LTC2158 to be programmed serially. The LTC2158 family
has the following options:
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