designed for digitizing high frequency, wide dynamic
range signals. It is perfect for demanding communications
applications with AC performance that includes 68.8dB
SNR and 88dB spurious free dynamic range (SFDR). The
1.25GHz input bandwidth allows the ADC to undersample
high frequencies with good performance. The latency is
only five clock cycles.
DC specs include ±1.2LSB INL (typ), ±0.35LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 2.11LSB
RMS
.
The digital outputs are double data rate (DDR) LVDS.
The ENC
+
and ENC
–
inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
68.8dBFS SNR
88dB SFDR
Low Power: 401mW Total
Single 1.8V Supply
DDR LVDS Outputs
Easy-to-Drive 1.32V
P-P
Input Range
1.25GHz Full Power Bandwidth S/H
Optional Clock Duty Cycle Stabilizer
Low Power Sleep and Nap Modes
Serial SPI Port for Configuration
Pin-Compatible 12-Bit Version
40-Lead (6mm × 6mm) QFN Package
applicaTions
n
n
n
n
n
n
Communications
Cellular Basestations
Software Defined Radios
Medical Imaging
High Definition Video
Testing and Measurement Instruments
Typical applicaTion
V
DD
OV
DD
D12_13
•
•
•
D0_1
LTC2153-14 32K Point 2-Tone FFT,
f
IN
= 71MHz and 69MHz, 310Msps
0
DDR
LVDS
AMPLITUDE (dBFS)
–20
–40
–60
–80
ANALOG
INPUT
S/H
14-BIT
PIPELINED
ADC
CORRECTION
LOGIC
OUTPUT
DRIVERS
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
OGND
GND
215314 TA01a
–100
–120
0
20
40
60 80 100 120 140
FREQUENCY (MHz)
215314 TA01b
215314f
1
LTC2153-14
absoluTe MaxiMuM raTings
(Notes 1, 2)
pin conFiguraTion
TOP VIEW
PAR/SER
D12_13
+
D12_13
–
D10_11
+
D2_3
+
D10_11
–
30 OV
DD
29 D8_9
+
28 D8_9
–
27 CLKOUT
+
41
GND
26 CLKOUT
–
25 D6_7
+
24 D6_7
–
23 D4_5
+
22 D4_5
–
21 OGND
11 12 13 14 15 16 17 18 19 20
GND
D2_3
–
D0_1
D0_1
OV
DD
ENC
+
ENC
–
–
OF
+
–
UJ PACKAGE
40-LEAD (6mm
×
6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 34°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC2153CUJ-14#PBF
LTC2153IUJ-14#PBF
TAPE AND REEL
LTC2153CUJ-14#TRPBF
LTC2153IUJ-14#TRPBF
PART MARKING*
LTC2153UJ-14
LTC2153UJ-14
PACKAGE DESCRIPTION
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
OF
+
Supply Voltage
V
DD
, OV
DD
................................................ –0.3V to 2V
Analog Input Voltage
A
IN+
, A
IN –
, PAR/SER,
SENSE (Note 3)........................ –0.3V to (V
DD
+ 0.2V)
Digital Input Voltage
ENC
+
, ENC
–
(Note 3) ................ –0.3V to (V
DD
+ 0.3V)
CS,
SDI, SCK (Note 4)........................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTC2153C ................................................ 0°C to 70°C
LTC2153I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
40 39 38 37 36 35 34 33 32 31
V
DD
1
V
DD
2
GND 3
A
IN+
4
A
IN–
5
GND 6
SENSE 7
VREF 8
VCM 9
GND 10
GND
SDO
SCK
SDI
CS
215314f
2
LTC2153-14
converTer characTerisTics
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
l
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Transition Noise
MIN
14
–7.5
–1
–15
–4.5
l
l
l
l
TYP
±1.2
±0.35
±5
±1.5
±1
±20
±30
±10
2.11
MAX
7.5
1
15
3
UNITS
Bits
LSB
LSB
mV
%FS
%FS
µV/°C
ppm/°C
ppm/°C
LSB
RMS
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
Internal Reference
External Reference
Internal Reference
External Reference
analog inpuT
SYMBOL PARAMETER
V
IN
V
IN(CM)
V
SENSE
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.74V < V
DD
< 1.9V
Differential Analog Input (Note 8)
0 < A
IN+
, A
IN–
< V
DD
, No Encode
0 < PAR/SER < V
DD
1.23V < SENSE < 1.27V
l
l
l
l
l
l
MIN
V
CM
– 20mV
1.230
–1
–1
–1
TYP
1.32
V
CM
1.250
MAX
V
CM
+ 20mV
1.270
1
1
1
UNITS
V
P-P
V
V
µA
µA
µA
ns
ps
RMS
dB
MHz
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
Analog Input Leakage Current
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
External Voltage Reference Applied to SENSE External Reference Mode
1
0.15
75
1250
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
CONDITIONS
15MHz Input
70MHz Input
140MHz Input
15MHz Input
70MHz Input
140MHz Input
15MHz Input
70MHz Input
140MHz Input
15MHz Input
70MHz Input
140MHz Input
MIN
TYP
68.8
68.4
67.7
88
85
79
98
95
90
68.7
68.4
67.2
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
DynaMic accuracy
l
66
SFDR
Spurious Free Dynamic Range 2nd or 3rd
Harmonic
Spurious Free Dynamic Range 4th Harmonic
or Higher
l
70
l
80
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
l
65
215314f
3
LTC2153-14
inTernal reFerence characTerisTics
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400µA < I
OUT
< 1mA
1.74V < V
DD
< 1.9V
–1mA < I
OUT
< 1mA
I
OUT
= 0
1.225
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
MIN
0.439 •
V
DD
– 18mV
TYP
0.439 •
V
DD
±37
4
1.250
±30
7
0.6
1.275
MAX
0.439 •
V
DD
+ 18mV
UNITS
V
ppm/°C
Ω
V
ppm/°C
Ω
mV/V
power requireMenTs
SYMBOL PARAMETER
V
DD
OV
DD
I
VDD
I
OVDD
P
DISS
P
SLEEP
P
NAP
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
Power Dissipation
Sleep Mode Power
Nap Mode Power
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
(Note 9)
(Note 9)
1.75mA LVDS Mode
3.5mA LVDS Mode
1.75mA LVDS Mode
3.5mA LVDS Mode
Clock Disabled
Clocked at f
S(MAX)
Clocked at f
S(MAX)
l
l
l
l
l
l
l
MIN
1.74
1.74
TYP
1.8
1.8
190
33
53
401
437
<5
<5
124
MAX
1.9
1.9
206
40
60
443
479
UNITS
V
V
mA
mA
mA
mW
mW
mW
mW
mW
DigiTal inpuTs anD ouTpuTs
SYMBOL
V
ID
V
ICM
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
R
OL
I
OH
C
OUT
PARAMETER
Differential Input Voltage
Common Mode Input Voltage
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
ENCODE INPUTS (ENC
+
, ENC
–
)
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
(Note 8)
Internally Set
Externally Set (Note 8)
(See Figure 2)
(Note 8)
V
DD
= 1.8V
V
DD
= 1.8V
V
IN
= 0V to 3.6V
(Note 8)
V
DD
= 1.8V, SDO = 0V
SDO = 0V to 3.6V
(Note 8)
l
l
l
l
l
l
MIN
0.2
1.1
TYP
MAX
UNITS
V
1.2
10
2
1.5
V
V
kΩ
pF
V
DIGITAL INPUTS (CS, SDI, SCK)
1.3
0.6
–10
3
200
–10
4
10
10
V
µA
pF
Ω
µA
pF
215314f
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
4
LTC2153-14
DigiTal inpuTs anD ouTpuTs
SYMBOL PARAMETER
DIGITAL DATA OUTPUTS
V
OD
V
OS
R
TERM
Differential Output Voltage
Common Mode Output Voltage
On-Chip Termination Resistance
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OV
DD
= 1.8V
l
l
l
l
MIN
247
125
1.125
1.125
TYP
350
175
1.250
1.250
100
MAX
454
250
1.375
1.375
UNITS
mV
mV
V
V
Ω
TiMing characTerisTics
f
S
t
L
t
H
Sampling Frequency
ENC Low Time (Note 8)
ENC High Time (Note 8)
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
(Note 9)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
l
l
l
MIN
10
1.5
1.2
1.5
1.2
TYP
1.61
1.61
1.61
1.61
MAX
310
50
50
50
50
UNITS
MHz
ns
ns
ns
ns
DIGITAL DATA OUTPUTS
MIN
t
D
t
C
t
SKEW
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
SPI Port Timing (Note 8)
t
SCK
t
S
t
H
t
DS
t
DH
t
DO
SCK Period
CS
to SCK Set-Up Time
SCK to
CS
Hold Time
SDI Set-Up Time
SDI Hold Time
SCK Falling to SDO Valid
Readback Mode, C
SDO
= 20pF, R
PULLUP
= 2k
Write Mode
Readback Mode C
SDO
= 20pF, R
PULLUP
= 2k
l
l
l
l
l
l
l
TYP
2
1.6
0.4
MAX
2.3
2
0.55
5
UNITS
ns
ns
ns
Cycles
ns
ns
ns
ns
ns
ns
C
L
= 5pF (Note 8)
C
L
= 5pF (Note 8)
t
D
– t
C
(Note 8)
l
l
l
1.7
1.3
0.3
5
40
250
5
5
5
5
125
ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3:
When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
DD
without latchup.
Note 4:
When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V
DD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5:
V
DD
= OV
DD
= 1.8V, f
SAMPLE
= 310MHz, differential ENC
+
/ENC
–
=
2V
P-P
sine wave, input range = 1.32V
P-P
with differential drive, unless
otherwise noted.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7:
Offset error is the offset voltage measured from –0.5LSB when the
output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111
FPGA/CPLD
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