Si5323
P
I N
- P
ROGRAMMABLE
P
R E C I S I O N
C
LOCK
M
ULTIPLIER
/J
I T T E R
A
TTENUA TOR
Features
Pin-selectable output frequencies
ranging from 8 kHz–708 MHz
Ultra-low jitter clock outputs as low
as 250 fs rms (12 kHz–20 MHz)
270 fs rms (50 kHz–80 MHz)
Integrated loop filter with selectable
loop bandwidth (60 Hz–8.4 kHz)
Meets ITU-T G.8251 and Telcordia
OC-192 GR-253-CORE jitter
specifications
Hitless input clock switching with
phase build-out and digital hold
Dual clock outputs with selectable
signal format (LVPECL, LVDS, CML,
CMOS)
Support for ITU G.709 FEC ratios
(255/238, 255/237, 255/236)
LOL, LOS alarm outputs
Pin-controlled output phase adjust
Single supply 1.8 ±5%, 2.5 or 3.3 V
±10% operation with high PSRR
On-chip voltage regulator
Small size: 6 x 6 mm 36-lead QFN
Ordering Information:
See page 33.
Applications
SONET/SDH OC-48/STM-16 and
OC-192/STM-64 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
Pin Assignments
ITU G.709 line cards
Optical modules
Test and measurement
Synchronous Ethernet
RST 1
FRQTBL
2
CKOUT1–
CKOUT2+
CKOUT2–
36 35 34 33 32 31 30 29 28
27 FRQSEL3
26 FRQSEL2
25 FRQSEL1
Description
The Si5323 is a jitter-attenuating precision clock multiplier for high-speed
communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz
and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to
1050 MHz. The input clock frequency and clock multiplication ratio are selectable
from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5323 is
based on Silicon Laboratories' 3rd-generation DSPLL
®
technology, which
provides any-frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and loop filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V
supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in
high performance timing applications.
C1B 3
C2B 4
VDD 5
XA 6
XB
7
NC
GND
CKOUT1+
24 FRQSEL0
23 BWSEL1
22 BWSEL0
21 CS_CA
20 INC
19 DEC
LOL
SFOUT0
GND
Pad
GND 8
AUTOSEL 9
10 11 12 13 14 15 16 17 18
CKIN2+
DBL2_BY
CKIN1+
CKIN1–
VDD
RATE0
CKIN2–
RATE1
Functional Block Diagram
Xtal or Refclock
CKIN1
CKOUT1
DSPLL
CKIN2
®
Signal Format
CKOUT2
Disable/BYPASS
Loss of Signal
Loss of Lock
Signal Detect
Control
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency Select
Bandwidth Select
Rate Select
Manual/Auto Switch
/
Clock Select
Skew Control
Rev. 1.0 1/11
Copyright © 2011 by Silicon Laboratories
SFOUT1
VDD
Si5323
Si5323
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . . .9
1.2. Three-Level Input Pins (Example with External Resistors) . . . . . . . . . . . . . . . . . . . . .9
2. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Pin Descriptions: Si5323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8. Si5323 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 1.0
3
Si5323
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
T
A
V
DD
Test Condition
3.3 V nominal
2.5 V nominal
1.8 V nominal
Min
–40
2.97
2.25
1.71
Typ
25
3.3
2.5
1.8
Max
85
3.63
2.75
1.89
Unit
ºC
V
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Supply Current
(Supply current is indepen-
dent of V
DD
)
Symbol
I
DD
Test Condition
LVPECL Format
622.08 MHz Out
All CKOUTs Enabled
1
LVPECL Format
622.08 MHz Out
Only 1 CKOUT Enabled
1
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
CMOS Format
19.44 MHz Out
Only CKOUT1 Enabled
1.8 V ±5%
2.5 V ±10%
3.3 V ±10%
Min
—
Typ
251
Max
279
Units
mA
—
217
243
mA
—
204
234
mA
—
194
220
mA
CKIN Input Pins
Input Common Mode
Voltage
(Input Threshold Voltage)
Input Resistance
Input Voltage Level Limits
Single-ended Input Voltage
Swing
V
ICM
0.9
1.0
1.1
20
0
0.2
0.25
—
—
—
40
—
—
—
1.4
1.7
1.95
60
V
DD
—
—
V
V
V
k
V
V
PP
V
PP
CKN
RIN
CKN
VIN
V
ISE
Single-ended
See note
2
f
CKIN
< 212.5 MHz
See Figure 2.
f
CKIN
> 212.5 MHz
See Figure 2.
Notes:
1.
LVPECL outputs require nominal V
DD
> 2.5 V.
2.
No overshoot or undershoot.
3.
This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
4
Rev. 1.0
Si5323
Table 2. DC Characteristics (Continued)
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Differential Input
Voltage Swing
Symbol
V
ID
Test Condition
f
CKIN
< 212.5 MHz
See Figure 2.
f
CKIN
> 212.5 MHz
See Figure 2.
Min
0.2
0.25
Typ
—
—
Max
—
—
Units
V
PP
V
PP
Output Clocks (CKOUTn)
1
Common Mode
Differential Output Swing
Single-ended Output Swing
Differential Output Voltage
Common Mode
Output Voltage
Differential
Output Voltage
CKO
VCM
CKO
VD
CKO
VSE
CKO
VD
CKO
VCM
CKO
VD
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
CML 100
load
line-to-line
CML 100
load
line-to-line
LVDS 100
load
line-to-line
Low swing LVDS 100
load
line-to-line
Common Mode
Output Voltage
Differential Output
Resistance
Output Voltage Low
Output Voltage High
Output Drive Current
CKO
VCM
CKO
RD
CKO
VOLLH
CKO
VOHLH
CKO
IO
LVDS 100
load
line-to-line
CML, LVDS, LVPECL
CMOS
V
DD
= 1.71 V
CMOS
CMOS
Driving into CKO
VOL
for out-
put low or CKO
VOH
for output
high. CKOUT+ and CKOUT–
shorted externally.
V
DD
= 1.8 V
V
DD
= 3.3 V
—
—
7.5
32
—
—
mA
mA
V
DD
–
1.42
1.1
0.5
350
—
500
350
1.125
—
—
0.8 x V
DD
—
—
—
425
V
DD
–
0.36
700
425
1.2
200
—
—
V
DD
–
1.25
1.9
0.93
500
—
900
500
1.275
—
0.4
—
V
V
PP
V
PP
mV
PP
V
mV
PP
mV
PP
V
V
V
Notes:
1.
LVPECL outputs require nominal V
DD
> 2.5 V.
2.
No overshoot or undershoot.
3.
This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
Rev. 1.0
5
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