Si5318
SONET/SDH P
R E C I S I O N
C
L O C K
M
U L T I P L I E R
I C
Features
Jitter generation as low as
0.7 ps
RMS
(typ), compliant with
GR-253-CORE OC-48
specifications
No external components
(other than a resistor and
standard bypassing)
Input clock ranges at 19, 39, 78,
and 155 MHz
Output clock ranges at 19 or
155 MHz
Digital hold for loss of input clock
Selectable loop bandwidth
Loss-of-signal alarm output
Low power
Small size (9x9 mm)
Si5318
Si5318
Applications
SONET/SDH line/port cards
Optical modules
Core switches
Digital cross connects
Terabit routers
Ordering Information:
See page 26.
Description
The Si5318 is a precision clock multiplier designed to exceed the requirements of
high-speed communication systems, including OC-48. The device phase locks to
an input clock in the 19, 39, 78, or 155 MHz frequency range and generates a low
jitter output clock in the 19 or 155 MHz range. Silicon Laboratories’ DSPLL®
technology delivers all PLL functionality with unparalleled performance while
eliminating external loop filter components, providing programmable loop
parameters, and simplifying design. The Si5318 establishes a new standard in
performance and integration for ultra-low-jitter clock generation. It operates from a
single 3.3 V supply.
Functional Block Diagram
REXT
VDD
GND
Biasing & Supply Regulation
FXDDELAY
CLKIN+
CLKIN–
VALTIME
LOS
2
CAL_ACTV
÷
Signal
Detect
3
DSPLL
®
DH_ACTV
÷
Calibration
2
CLKOUT+
CLKOUT–
FRQSEL[1:0]
RSTN/CAL
2
INFRQSEL[2:0]
BWSEL[1:0]
DBLBW
Rev. 1.0 4/05
Copyright © 2005 by Silicon Laboratories
Si5318
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5318
N
OTES
:
2
Rev. 1.0
Si5318
T
A B L E
Section
OF
C
O N T E N TS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1. DSPLL
®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.6. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3. Pin Descriptions: Si5318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Rev. 1.0
3
Si5318
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5318 Supply Voltage
3
Symbol
T
A
V
DD33
Test Condition
Min
1
–20
2
3.135
Typ
25
3.3
Max
1
85
3.465
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2.
The Si5318 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient
temperature of –20 to 85° C.
3.
The Si5318 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of Figure 5 on page 13.
4
Rev. 1.0
Si5318
CLKIN+
CLKIN–
V
IS
A. Operation with Single-Ended Clock Input
Note: When using single-ended clock sources, the unused clock
input on the Si5318 must be ac-coupled to ground.
CLKIN+
CLKIN–
0.5 V
ID
(CLKIN+) – (CLKIN–)
V
ID
B. Operation with Differential Clock Input
Note: Transmission line termination, when required, must be provided
externally
.
Figure 1. CLKIN Voltage Characteristics
80%
20%
t
F
t
R
Figure 2. Rise/Fall Time Measurement
(C L K IN + ) – (C L K IN – )
0 V
t
LOS
Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition
Rev. 1.0
5
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