signed for digitizing high frequency, wide dynamic range
signals. It is perfect for demanding communications ap-
plications with AC performance that includes 73.1dB SNR
and 88dB spurious free dynamic range (SFDR). Ultralow
jitter of 0.17ps
RMS
allows undersampling of IF frequencies
with excellent noise performance.
DC specs include ±4LSB INL (typical) and ±0.5LSB DNL
(typical).
The digital outputs can be either full-rate CMOS, double-
data rate CMOS, or double-data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
+
and ENC
–
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
73.1dB SNR
88dB SFDR
Low Power: 89mW
Single 1.8V Supply
CMOS, DDR CMOS or DDR LVDS Outputs
Selectable Input Ranges: 1V
P-P
to 2V
P-P
800MHz Full-Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
40-Pin (6mm
×
6mm) QFN Package
APPLICATIONS
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
TYPICAL APPLICATION
1.8V
V
DD
1.2V
TO 1.8V
OV
DD
2-Tone FFT, f
IN
= 70MHz and 75MHz
0
–10
–20
–30
AMPLITUDE (dBFS)
–40
–50
–60
–70
–80
+
ANALOG
INPUT
INPUT
S/H
–
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
D15
CMOS
•
OR
•
LVDS
•
D0
OGND
CLOCK/DUTY
CYCLE
CONTROL
GND
225916 TA01a
–90
–100
–110
–120
0
10
20
30
FREQUENCY (MHz)
40
225916 TA01b
80MHz
CLOCK
225916fa
1
LTC2259-16
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (V
DD
, OV
DD
) ....................... –0.3V to 2V
Analog Input Voltage (A
IN+
, A
IN –
,
PAR/SER, SENSE) (Note 3) .......... –0.3V to (V
DD
+ 0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range:
LTC2259C ................................................ 0°C to 70°C
LTC2259I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
PIN CONFIGURATION
D14_15
D12_13
SENSE
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
V
REF
V
CM
D15
D14
D13
D12
V
DD
D1
D0
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
SENSE
D0_1
V
REF
DNC
DNC
DNC
30 D10_11
29 DNC
28 CLKOUT
+
27 CLKOUT
–
41
GND
26 OV
DD
25 OGND
24 D8_9
23 DNC
22 D6_7
21 DNC
11 12 13 14 15 16 17 18 19 20
CS
SCK
DNC
D2_3
DNC
SDI
SDO
D4_5
ENC
+
ENC
–
V
CM
V
DD
30 D11
29 D10
28 CLKOUT
+
27
41
GND
CLKOUT
–
A
IN+
1
A
IN–
2
GND 3
REFH 4
REFH 5
REFL 6
REFL 7
PAR/SER 8
V
DD
9
V
DD
10
26 OV
DD
25 OGND
24 D9
23 D8
22 D7
21 D6
11 12 13 14 15 16 17 18 19 20
CS
SCK
SDO
SDI
D2
D3
D4
ENC
+
ENC
–
D5
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
D14_15
+
D14_15
–
D12_13
+
D12_13
–
SENSE
DO_1
+
D0_1
–
V
REF
V
CM
V
DD
40 39 38 37 36 35 34 33 32 31
A
IN
+
40 39 38 37 36 35 34 33 32 31
A
IN
A
IN
+
–
40 39 38 37 36 35 34 33 32 31
1
2
GND 3
REFH 4
REFH 5
REFL 6
REFL 7
PAR/SER 8
V
DD
9
V
DD
10
UJ PACKAGE
40-LEAD (6mm 6mm) PLASTIC QFN
UJ PACKAGE
40-LEAD (6mm 6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
1
30 D10_11
+
29 D10_11
–
28 CLKOUT
+
27 CLKOUT
–
41
GND
26 OV
DD
25 OGND
24 D8_9
+
23 D8_9
–
22 D6_7
+
21 D6_7
–
11 12 13 14 15 16 17 18 19 20
CS
SCK
ENC
+
ENC
–
SDO
SDI
D2_3
–
D2_3
+
D4_5
–
D4_5
+
A
IN–
2
GND 3
REFH 4
REFH 5
REFL 6
REFL 7
PAR/SER 8
V
DD
9
V
DD
10
UJ PACKAGE
40-LEAD (6mm 6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
225916fa
2
LTC2259-16
ORDER INFORMATION
LEAD FREE FINISH
LTC2259CUJ-16#PBF
LTC2259IUJ-16#PBF
TAPE AND REEL
LTC2259CUJ-16#TRPBF
LTC2259IUJ-16#TRPBF
PART MARKING*
LTC2259UJ-16
LTC2259UJ-16
PACKAGE DESCRIPTION
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
l
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Transition Noise
MIN
16
–12
–1
–9
–1.5
l
l
l
l
TYP
±4
±0.5
±1.5
±1.5
±0.4
±20
±30
±10
5
MAX
12
1.2
9
1.5
UNITS
Bits
LSB
LSB
mV
%FS
%FS
μV/°C
ppm/°C
ppm/°C
LSB
RMS
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
Internal Reference
External Reference
Internal Reference
External Reference
External Reference
ANALOG INPUT
SYMBOL PARAMETER
V
IN
V
INCM
V
SENSE
I
INCM
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
Per Pin, 80Msps
0 < A
IN+
, A
IN–
< V
DD
, No Encode
0 < PAR/SER < V
DD
0.625 < SENSE < 1.3V
l
l
l
l
l
l
MIN
V
CM
– 100mV
0.625
–1
–3
–6
TYP
1 to 2
V
CM
1.250
100
MAX
V
CM
+ 100mV
1.300
1
3
6
UNITS
V
P-P
V
V
μA
μA
μA
μA
ns
ps
RMS
dB
MHz
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
Analog Input Common Mode Current
Analog Input Leakage Current
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
External Voltage Reference Applied to SENSE External Reference Mode
0
0.17
80
Figure 6 Test Circuit
800
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
CONDITIONS
5MHz Input
70MHz Input
140MHz Input
l
DYNAMIC ACCURACY
MIN
70.9
TYP
73.1
72.9
72.4
MAX
UNITS
dBFS
dBFS
dBFS
225916fa
3
LTC2259-16
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
SYMBOL
SFDR
PARAMETER
Spurious Free Dynamic Range 2nd or 3rd
Harmonic
Spurious Free Dynamic Range 4th Harmonic or
Higher
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
CONDITIONS
5MHz Input
70MHz Input
140MHz Input
5MHz Input
70MHz Input
140MHz Input
5MHz Input
70MHz Input
140MHz Input
l
DYNAMIC ACCURACY
MIN
79
TYP
88
85
82
90
90
90
72.9
72.6
72
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
l
85
l
70.4
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400μA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600μA < I
OUT
< 1mA
I
OUT
= 0
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
MIN
0.5 • V
DD
– 25mV
TYP
0.5 • V
DD
±25
4
1.225
1.250
±25
7
0.6
1.275
MAX
0.5 • V
DD
+ 25mV
UNITS
V
ppm/°C
Ω
V
ppm/°C
Ω
mV/V
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER
ENCODE INPUTS (ENC
+
, ENC
–
)
Differential Encode Mode (ENC
–
Not Tied to GND)
V
ID
V
ICM
V
IN
R
IN
C
IN
V
IH
V
IL
V
IN
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
(Note 8)
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
0.2
1.2
1.1
0.2
10
3.5
1.6
3.6
V
V
V
V
kΩ
pF
V
0.6
V
V
kΩ
pF
V
0.6
V
μA
pF
225916fa
Internally Set
Externally Set (Note 8)
ENC
+
, ENC
–
to GND
(See Figure 10)
(Note 8)
V
DD
= 1.8V
V
DD
= 1.8V
ENC
+
to GND
(See Figure 11)
(Note 8)
V
DD
= 1.8V
V
DD
= 1.8V
V
IN
= 0V to 3.6V
(Note 8)
Single-Ended Encode Mode (ENC
–
Tied to GND)
l
l
l
1.2
0
30
3.5
3.6
DIGITAL INPUTS (CS, SDI, SCK)
l
l
l
1.3
–10
3
10
4
LTC2259-16
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER
R
OL
I
OH
C
OUT
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
V
DD
= 1.8V, SDO = 0V
SDO = 0V to 3.6V
(Note 8)
l
MIN
TYP
200
MAX
UNITS
Ω
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
–10
4
10
μA
pF
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE-DATA RATE)
OV
DD
= 1.8V
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OD
V
OS
R
TERM
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
Differential Output Voltage
Common Mode Output Voltage
On-Chip Termination Resistance
I
O
= –500μA
I
O
= 500μA
I
O
= –500μA
I
O
= 500μA
I
O
= –500μA
I
O
= 500μA
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OV
DD
= 1.8V
l
l
l
l
1.750
1.790
0.010
1.488
0.010
1.185
0.010
0.050
V
V
V
V
V
V
454
1.375
mV
mV
V
V
Ω
OV
DD
= 1.5V
OV
DD
= 1.2V
DIGITAL DATA OUTPUTS (LVDS MODE)
247
1.125
350
175
1.250
1.250
100
POWER REQUIREMENTS
SYMBOL
V
DD
OV
DD
I
VDD
I
OVDD
P
DISS
PARAMETER
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
Power Dissipation
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 9)
CONDITIONS
(Note 10)
(Note 10)
DC Input
Sine Wave Input
Sine Wave Input, OV
DD
=1.2V
DC Input
Sine Wave Input, OV
DD
=1.2V
(Note 10)
(Note 10)
Sine Wave Input
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
l
l
MIN
1.7
1.1
TYP
1.8
49.2
50.2
2.5
89
93
MAX
1.9
1.9
58.1
UNITS
V
V
mA
mA
mA
mW
mW
V
V
mA
mA
mA
mW
mW
mW
mW
mW
225916fa
CMOS Output Modes: Full Data Rate and Double-Data Rate
105
LVDS Output Mode
V
DD
OV
DD
I
VDD
I
OVDD
P
DISS
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
(0V
DD
= 1.8V)
Power Dissipation
l
l
l
l
l
l
l
1.7
1.7
1.8
53.8
20.7
40.5
134
170
0.5
9
10
1.9
1.9
63.5
26
47.8
161
201
All Output Modes
P
SLEEP
P
NAP
P
DIFFCLK
Sleep Mode Power
Nap Mode Power
Power Increase with Differential Encode Mode Enabled
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