DATASHEET
FRAME RATE COMMUNICATIONS PLL
Description
The MK1574-01A/B are Phase-Locked Loop (PLL) based
clock synthesizers, which accept an 8 kHz clock input as a
reference, and generate many popular communications
frequencies. All outputs are frequency locked together and
to the input. This allows for the generation of locked clocks
to the 8 kHz backplane clock, simplifying clock generation
and distribution in communications systems.
1) MK1574-01A — 5 V operation
2) MK1574-01B — 3.3 V operation
IDT manufactures the largest variety of clock generators
and buffers, and can customize this device for a variety of
frequencies.
MK1574-01A/B
Features
•
•
•
•
Packaged in 16-pin SOIC
Accepts 8 kHz input clock
Output clock rates include T1, E1, T2, E2
Available in commercial (0º to + 70ºC) or industrial (-40 to
+85ºC) temperature ranges
•
For jitter attenuation, use the MK2049
Block Diagram
VDD
GND
2
2
CLK1
FS0-3
4
8 kHz
input
clock
Input
Buffer
PLL Clock
Synthesis
and Control
Circuitry
CLK2
CLK3
8 kHz
(recovered)
CAP1
CAP2
IDT™ / ICS™
FRAME RATE COMMUNICATIONS PLL
1
MK1574-01A/B
REV D 051310
MK1574-01A/B
FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
Pin Assignment
ICLK
VDD
VDD
CAP1
GND
CAP2
GND
FS0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS3
NC
FS2
FS1
CLK3
CLK2
CLK1
8KOUT
Output Clocks Decoding Table
Decode
FS3:0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Address
(Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ICLK
pin1
Reserved
Reserved
Reserved
Reserved
8.00 kHz
8.00 kHz
8.00 kHz
8.00 kHz
8.00 kHz
8.00 kHz
8.00 kHz
8.00 kHz
8.00 kHz
8.00 kHz
8.00 kHz
8.00 kHz
Multiplier
On-chip
Reserved
Reserved
Reserved
Reserved
2940
1960
2760
2640
1920
6480
2112
1578
8192
6176
1024
772
CLK1
pin 10
Reserved
Reserved
Reserved
Reserved
23.52
15.68
22.08
21.12
15.36
51.84
16.896
12.624
65.536
49.408
8.192
60176
CLK2
pin 11
Reserved
Reserved
Reserved
Reserved
11.76
7.84
11.04
10.56
7.68
25.92
8.448
6.312
32.768
24.704
4.096
3.088
CLK3
pin 12
Reserved
Reserved
Reserved
Reserved
5.88
3.92
5.52
5.28
3.84
12.96
4.224
3.156
16.384
12.352
2.048
1.544
0 = connect directly to ground, 1 = connect directly to VDD.
IDT™ / ICS™
FRAME RATE COMMUNICATIONS PLL
2
MK1574-01A/B
REV D 051310
MK1574-01A/B
FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
Pin Descriptions
Pin
Number
1
2
3
4
Pin
Name
ICLK
VDD
VDD
CAP1
Pin
Type
Input
Power
Power
Input
Pin Description
Clock input. Connect to an 8 kHz clock input.
Connect to 3.3 V for 1574-01B, Connect to 5 V for 1574-01A.
Connect to 3.3 V for 1574-01B, Connect to 5 V for 1574-01A.
Connect to a ceramic capacitor and a resistor in series between this pin and
CAP2. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
Connect to ground.
Connect to a ceramic capacitor and a resistor in series between this pin and
CAP1. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
Connect to ground.
Frequency select 0. Determines CLK outputs per table above.
5
6
GND
CAP2
Power
Power
7
8
9
10
11
12
13
14
15
16
GND
FS0
8KOUT
CLK1
CLK2
CLK3
FS1
FS2
NC
FS3
Power
Input
Output Recovered 8 kHz output clock. Can be low jitter, better duty cycle than clock
input.
Output Clock 1 determined by status of FS3:0 per table above.
Output Clock 2 determined by status of FS3:0 per table above.
Output Clock 3 determined by status of FS3:0 per table above.
Input
Input
—
Input
Frequency select 1. Determines CLK outputs per table above.
Frequency select 2. Determines CLK outputs per table above.
No connect. Do not connect anything to this pin.
Frequency select 3. Determines CLK outputs per table above.
External Components
The MK1574-01A/B requires a minimum number of external components for proper operation. An RC network (see
the section “Loop Bandwidth and Loop Filter Component Selection”) should be connected between CAP1 and
CAP2 as close tot he device as possible. Decoupling capacitors of 0.01µF should be connected between VDD and
GND on pins 2, 3, 5 and 7, as close to the device as possible. A series termination resistor of 33Ω may be used
close to each clock output pin to reduce reflections.
IDT™ / ICS™
FRAME RATE COMMUNICATIONS PLL
3
MK1574-01A/B
REV D 051310
MK1574-01A/B
FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1574-01A/B. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD (referenced to GND)
All Inputs and Outputs
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
-0.5 V to 7 V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
+3.13
Typ.
Max.
+70
+85
+5.5
Units
°
C
°
C
V
IDT™ / ICS™
FRAME RATE COMMUNICATIONS PLL
4
MK1574-01A/B
REV D 051310
MK1574-01A/B
FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
DC Electrical Characteristics
MK1574-01A
VDD = 5 V,
Ambient temperature 0 to +70° C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Operating Supply
Current
Short Circuit Current
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OH
V
OL
IDD
I
OS
C
IN
Conditions
Min.
4.5
2
Typ.
Max.
5.5
0.8
Units
V
V
V
V
V
I
OH
= -4 mA
I
OH
= -25 mA
I
OL
= 25 mA
No Load
Each output
VDD-0.4
2.4
0.4
15
±100
7
V
mA
mA
pF
MK1574-01B
VDD = 3.3 V,
Ambient temperature 0 to +70° C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Operating Supply
Current
Short Circuit Current
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OH
V
OL
IDD
I
OS
C
IN
Conditions
Min.
3.0
2
Typ.
Max.
3.6
0.8
Units
V
V
V
V
V
I
OH
= -4 mA
I
OH
= -25 mA
I
OL
= 25 mA
No Load
Each output
VDD-0.4
2.4
0.4
13
±100
7
V
mA
mA
pF
IDT™ / ICS™
FRAME RATE COMMUNICATIONS PLL
5
MK1574-01A/B
REV D 051310
嵌入式系统
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