CH
www.vishay.com
Vishay Sfernice
High Frequency 50 GHz Thin Film Chip Resistor
FEATURES
• Operating frequency 50 GHz
• Thin film microwave resistors
• SMD wraparound or flip chip resistor
• Small size, down to 20 mils by 16 mils
• Edged trimmed block resistors
• Pure alumina substrate (99.5 %)
• Ohmic range: 10R to 500R
• Design kits available
• Small internal reactance (LC down to 1 × 10
-24
)
• Tolerance 1 %, 2 %, 5 %, 10 %
• TCR: 100 ppm/°C in (- 55 °C, + 155 °C) temperature range
Those miniaturized components are designed in such a way
that their internal reactance is very small. When correctly
mounted and utilized, they function as almost pure resistors
on a very large range of frequency, up to 50 GHz.
• Material categorization: For definitions of compliance
please see
www.vishay.com/doc?99912
STANDARD ELECTRICAL SPECIFICATIONS
MODEL
CH02016
CH0402
CH0603
SIZE
02016
0402
0603
RESISTANCE
RANGE
10 to 500
10 to 500
10 to 500
RATED POWER
Pn
W
0.030
0.050
0.125
LIMITING
ELEMENT
VOLTAGE
V
30
37
50
TOLERANCE
±%
1, 2, 5, 10
1, 2, 5, 10
1, 2, 5, 10
TEMPERATURE
COEFFICIENT
± ppm/°C
100
100
100
DIMENSIONS
in millimeters (inches)
A
D
D
C
D
A
(1)
D
C
D
A
D
C
E
E
B
(F)
CASE SIZE
MAX. TOL.
+ 0.1 (+ 0.004)
MIN. TOL.
- 0.1 (- 0.004)
02016
0402
0603
(P)
(N) and (G)
DIMENSIONS
A
(1)
MAX. TOL.
+ 0.1 (+ 0.004)
MIN. TOL.
- 0.1 (- 0.004)
0.48 (0.020)
1.00 (0.040)
1.52 (0.060)
B
MAX. TOL.
+ 0.1 (+ 0.004)
MIN. TOL.
- 0.1 (- 0.004)
0.39 (0.016)
0.6 (0.023)
0.75 (0.030)
C
MAX. TOL.
+ 0.127 (+ 0.005)
MIN. TOL.
- 0.127 (- 0.005)
0.42 (0.02)
(2)
0.5 (0.02)
0.5 (0.02)
MIN.
0.11 (0.004)
0.15 (0.006)
0.25 (0.010)
D/E
MAX.
0.15 (0.008)
0.35 (0.014)
0.51 (0.020)
Notes
(1)
For CH0402 and CH0603 with P termination, A dimension is increased by 0.2 mm
(2)
+ or - 0.07 mm
Revision: 28-Aug-13
Document Number: 53014
1
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH
www.vishay.com
Vishay Sfernice
LAND PATTERN FLIP CHIP TERMINATIONS
in millimeters
G
min.
X
max.
Z
max.
CHIP SIZE
02016
0402
0603
Z
max.
0.53
1.4
1.71
X
max.
0.44
0.650
0.9
G
min.
0.15
0.4
0.760
Note
• Suggested land pattern: According to IPC-7351
Dimension and tolerance of land pattern shall be defined by PCB designer; PCB can be designed according to IPC-7351A
“Generic Requirements for Surface Mount Design and Land Pattern Standard”
Example of land pattern: Fabrication allowance, assembly location and min. or max. level density board are not included in the
exemple bellow.
According to IPC-7351A “Generic Requirements for Surface Mount Design and Land Pattern Standard”:
Z
max.
= A
min.
+ 2J
T
+
G
min.
= F
max.
+ 2J
H
-
X
max.
= B
min.
+ 2J
S
+
C
A
+
F
+
P
with C: “Unilateral profile tolerance for the component”;
C
F
+
F
+
P
F: ”Unilateral profile tolerance for the board land pattern”;
C
B
+
F
+
P
and P: “Diameter of true position placement accuracy to the center of land pattern”.
J
H
2
2
2
2
2
2
2
2
2
J
S
For rectangular component
suggest:
JT (TOE)
Flip-Chip mounting, we
0 mm
0 mm
0 mm
COMPONENT
JH (HELL)
JS (SDE)
Land Pattern Footprint
J
T
WRAPAROUND TERMINATIONS
in millimeters
G
min.
Z
max.
CHIP SIZE
0402
0603
Z
max.
1.55
2.37
G
min.
0.15
0.35
X
m
ax
.
X
max.
0.73
0.98
TOLERANCE VS. OHMIC VALUES
Ohmic range
Tolerance
10
R
< 50
5 %, 10 %
50
R
< 100
2 %, 5 %, 10 %
100
R
500
(1)
1 %, 2 %, 5 %, 10 %
Note
(1)
Best tolerance for 100
to 500
in 02016 is 2 %
Revision: 28-Aug-13
Document Number: 53014
2
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH
www.vishay.com
PREFERRED MODELS AND VALUES
Vishay Sfernice highly recommend to use the smallest sizes and flip chip version to get the best performances.
Recommended Values:
10R/18R/25R/50R/75R/100R/150R/180R/200R/250R/330R/500R
Those values are available with a
MOQ of 100 pieces.
Other values can be ordered upon request, but higher MOQ will apply: 1000 pieces for CH02016, 500 pieces for CH0402,
50 pieces for CH0603.
Recommended terminations:
F
Recommended tolerance:
2%
Design kits
are available Ex Stock in CH02016 and CH0402 sizes. There are 20 pieces per recommended value. F termination.
5 % tolerance.
Those kits are packaged in pieces of tape and delivered in ESD bags.
Vishay Sfernice
PACKAGING
Standard packaging is waffle pack for sizes 0402 and 0603 and plastic tape and reel (low conductivity) for size 02016.
Paper tape and reel is available for size 0402 and either paper tape and reel or plastic tape and reel (low conductivity) for size
0603.
Depending on the type of terminations, parts will be packed differently:
One face:
• Gold terminations: Active face up
• Tin/silver termination: Active face down
Note
• Please refer to Vishay Sfernice Application Note “Guidelines for Vishay Sfernice Resistive and Inductive Products” for soldering
recommendation (document number 52029, 3. Guidelines for Surface Mounting Components (SMD), profile number 3 applies
NUMBER OF PIECES PER PACKAGE
SIZE
MOQ
WAFFLE PACK
2" X 2"
484
100
100
100
5000
8 mm
TAPE AND REEL
Min.
Max.
TAPE WIDTH
02016
0402
0603
See MOQ mentioned
on preferred models
and values
PACKAGING RULES
Waffle Pack
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered exceeds maximum quantity of a
single waffle pack, the waffle packs are stacked up on the
top of each other and closed by one single cover. To get
“not stacked up” waffle pack in case of ordered quantity
> maximum number of pieces per package: Please consult
Vishay Sfernice for specific ordering code.
Tape and Reel
See Part Numbering information to get the quantity desired
by tape.
Revision: 28-Aug-13
Document Number: 53014
3
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH
www.vishay.com
Vishay Sfernice
GLOBAL PART NUMBER INFORMATION
New Global Part Numbering: CH0402-50RJF (preferred part number format)
C
H
0
4
SIZE
02016
0402
0603
0
2
-
5
TOLERANCE
F
=1%
G
=2%
J
=5%
K
= 10 %
0
R
J
F
T
PACKAGING
9
9
9
GLOBAL MODEL
CH
OHMIC VALUE
10R to 500R
TERMINATION
(1)
F
(Flip Chip):
SnAg over nickel barrier
N
(W/A):
SnAg over nickel barrier
(except 02016)
P
(one face):
(2)
Gold bonding pads
G
(W/A): Gold
(except 02016)
OPTION
From
1 to 3 digits.
Leave blank
if no option.
For more
information see
Codification of
Packaging table
Historical Part Number example: CH02016-100RGFPT1K (tapes of 1K pieces)
CH0402-50RJF
(waffle pack)
Note
• Historical part numbers are not recommended but can still be used for ordering.
CODIFICATION OF PACKAGING
WAFFLE PACK (standard packaging for CH0402 and CH0603)
W
10 min., 1 mult
PLASTIC TAPE (standard packaging for CH02016 and CH0603)
T
100 min., 1 mult
TA
100 min., 100 mult
TB
250 min., 250 mult
TC
500 min., 500 mult
TD
1000 min., 1000 mult
TE
2500 min., 2500 mult
TF
Full tape (qunatity depending on size of chips)
PAPER TAPE (standard packaging for CH0402 - available for CH0603)
PT
100 min., 1 mult
PA
100 min., 100 mult
PB
250 min., 250 mult
PC
500 min., 500 mult
PD
1000 min., 1000 mult
PE
2500 min., 2500 mult
PF
Full tape (qunatity depending on size of chips)
TYPICAL HIGH FREQUENCY PERFORMANCE ELECTRICAL MODEL
Z
C
Z
0
L
c
L
R
L
c
C
g
Z
0
C
L
R
Z
L
c
C
g
Internal shunt capacitance
Internal inductance
Resistance
Internal impedance (R, L, C)
External connection inductance
External capacitance to ground
Revision: 28-Aug-13
Document Number: 53014
4
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH
www.vishay.com
The complex impedance of the chip resistor is given by the following equations:
R
+
j
L
–
R
C
–
L C
-
Z
=
-------------------------------------------------------------------------------------
2
2
2
4
1
+
C
R
C
–
2L
+
L C
Z
1
-
-------
=
-----------------------------------------------------------------------------------------
x
-
2
2
2
4
R
1
+
C
R
C
–
2L
+
L C
–
1
L
2
2
2
2
Vishay Sfernice
L
–
R
C
–
L C
-
1
+
-----------------------------------------------------------
R
2
2
2
2
2
2
Notes
•
=2x
x
f
•
f:
Frequency
–
R
C
–
L C
-
=
tan
-----------------------------------------------------------
R
L
The chip resistor itself is purely resistive when
R
=
---
. The smaller the L x C product the greater the frequency range over
-
C
which the resistor looks approximately resistive.
Z
-
This can be seen on the graphs showing the ratio
-------
versus frequency.
R
R, L and C are relevant to the chip resistor itself.
L
c
and C
g
also depends on the way the chip resistor is mounted.
It is important to notice that after assembly the external reactance of L
c
and C
g
will be combined to internal reactance of L and
C. This combination can upgrade or downgrade the HF behaviour of the component.
This is why we are displaying two sets of data:
Z
-
•
-------
versus frequency curves which aims to show at a glance the intrinsic HF performance of a given chip resistor
R
• S-parameters versus frequency curves relevant to chip resistor when assembled on ideal Z0 impedance transmission line
These lines are terminated with adapted source and load impedance respectively Z
s
and Z
l
with Z
0
= Z
L
= Z
s
(for others
configurations please consult us).
Equivalent circuit for S-parameters:
Z total
C
Z
S
Z
0
C
g
L
c
L
R
L
c
C
g
Z
0
Z
L
G
S-parameters are computed taking into account all the resistive, inductive and capacitive elements (Z total) and Z
0
= Z
L
= Z
s
=
R.
Revision: 28-Aug-13
Document Number: 53014
5
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
