V58C2512(804/404/164)SD
HIGH PERFORMANCE 512 Mbit DDR SDRAM
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 8Mbit X 16 (164)
4
DDR500
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
-
-
4ns
250 MHz
5
DDR400
7.5ns
6ns
5ns
200 MHz
6
DDR333
7.5ns
6ns
-
166 MHz
75
DDR266
-
7.5ns
-
133 MHz
Features
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-
-
-
-
-
Description
The V58C2512(804/404/164)SD is a four bank DDR
DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x
32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The
V58C2512(804/404/164)SD achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
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-
-
-
-
-
-
-
-
-
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High speed data transfer rates with system frequency
up to 250MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 60 Ball FBGA and 66 Pin TSOP II
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V
tRAS lockout supported
Concurrent auto precharge option is supported
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-40°C to 85°C
Package Outline
JEDEC 66 TSOP II
60 FBGA
•
•
CK Cycle Time (ns)
-4
•
•
Power
-75
•
•
-5
•
•
-6
•
•
Std.
•
•
L
•
•
Temperature
Mark
Blank
I
V58C2512(804/404/164)SD Rev.1.8 September 2010
1
模拟电子
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