54F 74F322 Octal Serial Parallel Register with Sign Extend
May 1995
54F 74F322
Octal Serial Parallel Register with Sign Extend
General Description
The ’F322 is an 8-bit shift register with provision for either
serial or parallel loading and with TRI-STATE parallel out-
puts plus a bi-state serial output Parallel data inputs and
parallel outputs are multiplexed to minimize pin count State
changes are initiated by the rising edge of the clock Four
synchronous modes of operation are possible hold (store)
shift right with serial entry shift right with sign extend and
parallel load An asynchronous Master Reset (MR) input
overrides clocked operation and clears the register
Features
Y
Y
Y
Y
Multiplexed parallel I O ports
Separate serial input and output
Sign extend function
TRI-STATE outputs for bus applications
Commercial
74F322PC
Military
Package
Number
N20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F322DM (Note 2)
74F322SJ (Note 1)
54F322FM (Note 2)
54F322LM (Note 2)
Note 1
Devices also available in 13 reel Use suffix
e
SJX
J20A
M20D
W20A
E20A
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9516 – 3
TL F 9516 – 5
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9516
RRD-B30M105 Printed in U S A
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9516 – 2
TL F 9516– 1
2
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
Input I
IH
I
IL
Output I
OH
I
OL
RE
S P
SE
S
D
0
D
1
CP
MR
OE
Q
0
I O
0
–I O
7
Register Enable Input (Active LOW)
10 10
20
mA
b
0 6 mA
Serial (HIGH) or Parallel (LOW) Mode Control Input
10 10
20
mA
b
0 6 mA
Sign Extend Input (Active LOW)
10 30
20
mA
b
1 8 mA
Serial Data Select Input
10 20
20
mA
b
1 2 mA
Serial Data Inputs
10 10
20
mA
b
0 6 mA
Clock Pulse Input (Active Rising Edge)
10 10
20
mA
b
0 6 mA
Asynchronous Master Reset Input (Active LOW)
10 10
20
mA
b
0 6 mA
TRI-STATE Output Enable Input (Active LOW)
10 10
20
mA
b
0 6 mA
b
1 mA
b
20 mA
Bi-State Serial Output
50 33 3
Multiplexed Parallel Data Inputs or
3 5 1 083
70
mA
b
0 65 mA
b
3 mA 24 mA (20 mA)
TRI-STATE Parallel Data Outputs
150 40 (33 3)
Functional Description
The ’F322 contains eight D-type edge triggered flip-flops
and the interstage gating required to perform right shift and
the intrastage gating necessary for hold and synchronous
parallel load operations A LOW signal on RE enables shift-
ing or parallel loading while a HIGH signal enables the hold
mode A HIGH signal on S P enables shift right while a
LOW signal disables the TRI-STATE output buffers and en-
ables parallel loading In the shift right mode a HIGH signal
on SE enables serial entry from either D
0
or D
1
as deter-
mined by the S input A LOW signal on SE enables shift right
but Q
7
reloads its contents thus performing the sign extend
function required for the ’F384 Twos Complement Multiplier
A HIGH signal on OE disables the TRI-STATE output buff-
ers regardless of the other control inputs In this condition
the shifting and loading operations can still be performed
Mode Select Table
Mode
MR
Clear
Parallel
Load
Shift
Right
Sign
Extend
Hold
L
L
H
H
H
H
H
RE
X
X
L
L
L
L
H
S P
X
X
L
H
H
H
X
Inputs
SE
X
X
X
H
H
L
X
S
X
X
X
L
H
X
X
OE
L
H
X
L
L
L
L
CP
X
X
L
L
L
L
L
I O
7
L
Z
I
7
D
0
D
1
O
7
NC
I O
6
L
Z
I
6
O
7
O
7
O
7
NC
I O
5
L
Z
I
5
O
6
O
6
O
6
NC
Outputs
I O
4
L
Z
I
4
O
5
O
5
O
5
NC
I O
3
L
Z
I
3
O
4
O
4
O
4
NC
I O
2
L
Z
I
2
O
3
O
3
O
3
NC
I O
1
L
Z
I
1
O
2
O
2
O
2
NC
I O
0
L
Z
I
0
O
1
O
1
O
1
NC
L
L
I
0
O
1
O
1
O
1
NC
Q
0
When the OE input is HIGH all I O
n
terminals are at the high impedance state sequential operation or clearing of the register is not affected
Note 1
I
7
–I
0
e
The level of the steady-state input at the respective I O terminal is loaded into the flip-flop while the flip-flop outputs (except Q
0
) are isolated from
the I O terminal
Note 2
D
0
D
1
e
The level of the steady-state inputs to the serial multiplexer input
Note 3
O
7
–O
0
e
The level of the respective Q
n
flip-flop prior to the last Clock LOW-to-HIGH transition
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
Z
e
High Impedance Output State
L
e
LOW-to-HIGH Transition
NC
e
No Change
3
Logic Diagram
TL F 9516 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
4
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
b
65 C to
a
150 C
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
b
0 5V to
a
7 0V
b
30 mA to
a
5 0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
b
0 5V to V
CC
b
0 5V to
a
5 5V
twice the rated I
OL
(mA)
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
54F 10% V
CC
54F 10% V
CC
74F 10% V
CC
74F 10% V
CC
74F 5% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
74F 10% V
CC
54F
74F
54F
74F
54F
74F
54F
74F
74F
74F
4 75
3 75
b
0 6
b
1 2
b
1 8
54F 74F
Typ
Max
Units
V
08
b
1 2
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
Min
I
IN
e b
18 mA
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
e
e
e
e
e
e
b
1 mA (Q
0
I O
n
)
b
3 mA (I O
n
)
b
1 mA (Q
0
I O
n
)
b
3 mA (I O
n
)
b
1 mA (Q
0
I O
n
)
b
3 mA (I O
n
)
25
24
25
24
27
27
05
05
05
20 0
50
100
70
10
05
250
50
V
Min
V
OL
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown Test (I O)
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
V
Min
I
OL
e
20 mA (Q
0
I O
n
)
I
OL
e
20 mA (Q
0
)
I
OL
e
24 mA ( I O
n
)
V
IN
e
2 7V
V
IN
e
7 0V (Non-I O Inputs)
V
IN
e
5 5V (I O
n
)
V
OUT
e
V
CC
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V (RE S P D
n
CP MR OE)
V
IN
e
0 5V (S)
V
IN
e
0 5V (SE)
V
I O
e
2 7V (I O
n
)
V
I O
e
0 5V (I O
n
)
V
OUT
e
0V
V
OUT
e
5 25V
I
IH
I
BVI
I
BVIT
I
CEX
V
ID
I
OD
I
IL
mA
mA
mA
mA
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
Max
Max
Max
Max
00
00
Max
Max
Max
Max
Max
Max
0 0V
Max
I
IH
a
I
OZH
I
IL
a
I
OZL
I
OS
I
ZZ
I
CC
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
60
b
60
70
b
650
b
150
500
90
5
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