54ACTQ543 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs
August 1998
54ACTQ543
Quiet Series Octal Registered Transceiver with
TRI-STATE
®
Outputs
General Description
The ACTQ543 is a non-inverting octal transceiver containing
two sets of D-type registers for temporary storage of data
flowing in either direction. Separate Latch Enable and Out-
put Enable inputs are provided for each register to permit in-
dependent input and output control in either direction of data
flow.
The ACTQ utilizes NSC Quiet Series technology to guaran-
tee quiet output switching and improved dynamic threshold
performance. FACT Quiet Series
™
features GTO
™
output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Features
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
8-bit octal latched transceiver
n
Separate controls for data flow in each direction
n
Back-to-back registers for storage
n
Outputs source/sink 24 mA
n
4 kV minimum ESD immunity
Ordering Code
Military
54ACTQ543DMQB
54ACTQ543FMQB
54ACTQ543LMQB
Package
Number
J24A
W24C
E28A
Package Description
24-Lead Ceramic Dual-In-Line
24-Lead Cerpack
24-Lead Ceramic Leadless
Chip Carrier, Type C
IEEE/IEC
Logic Symbols
DS100233-1
DS100233-4
GTO
™
is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
™
is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100233
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Connection Diagrams
Pin Assignment for
DIP and Flatpak
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A
0
–A
7
B
0
–B
7
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A TRI-STATE Outputs
B-to-A Data Inputs or
A-to-B TRI-STATE Outputs
Functional Description
DS100233-2
Pin Assignment
for LCC
The ACTQ543 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input
must be LOW in order to enter data from A
0
–A
7
or take data
from B
0
–B
7
, as indicated in the Data I/O Control Table. With
CEAB LOW, a LOW signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subse-
quent LOW-to-HIGH transition of the LEAB signal puts the A
latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both LOW,
the TRI-STATE B output buffers are active and reflect the
data present at the output of the A latches. Control of data
flow from B to A is similar, but using the CEBA, LEBA and
OEBA inputs.
Data I/O Control Table
DS100233-3
Inputs
CEAB LEAB OEAB
H
X
L
X
L
X
H
L
X
X
X
X
X
H
L
Latch Status
Latched
Latched
Transparent
—
—
Output Buffers
High Z
—
—
High Z
Driving
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using CEBA,
LEBA and OEBA
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2
Logic Diagram
DS100233-8
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
= V
CC
+ 0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
= V
CC
+ 0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
DC Latch-up Source or
Sink Current
Junction Temperature (T
J
)
CDIP
±
300 mA
175˚C
Recommended Operating
Conditions
Supply Voltage V
CC
’ACTQ
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
) (Note 2)
54ACTQ
Minimum Input Edge Rate
∆V/∆t
’ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−55˚C to +125˚C
±
50 mA
±
50 mA
−65˚C to +150˚C
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
®
circuits outside databook specifications.
Note 2:
All commercial packaging is not recommended for applications re-
quiring greater than 2000 temperature cycles from −40˚C to +125˚C.
DC Characteristics for ’ACTQ Family Devices
Symbol
Parameter
V
CC
(V)
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
4.5
5.5
4.5
5.5
4.5
5.5
54ACTQ
T
A
=
−55˚C to +125˚C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
(Note 3)
V
IN
= V
IL
or V
IH
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
3.70
4.70
0.1
0.1
(Note 3)
V
IN
= V
IL
or V
IH
4.5
5.5
I
IN
I
OZT
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum I/O
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current
(Note 4)
Maximum Quiescent
Supply Current
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4
Units
Conditions
V
V
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
OUT
= 0.1V
or V
CC
− 0.1V
I
OUT
= −50 µA
V
V
I
OH
= −24 mA
I
OH
= −24 mA
I
OUT
= 50 µA
0.50
0.50
V
µA
µA
mA
mA
I
OL
= 24 mA
I
OL
= 24 mA
V
I
= V
CC
, GND
V
(OE) =
V
IL
, V
IH
V
O
= V
CC
, GND
V
I
= V
CC
− 2.1V
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
V
IN
= V
CC
or GND (Note 5)
5.5
5.5
5.5
5.5
5.5
5.5
±
1.0
±
10
1.6
−50
160.0
mA
µA
DC Characteristics for ’ACTQ Family Devices
Symbol
Parameter
V
CC
(V)
V
OLP
V
OLV
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Note 3:
Maximum of 8 outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
I
CC
for 54ACTQ
@
25˚C is identical to 74ACTQ
@
25˚C.
Note 6:
Plastic DIP package.
(Continued)
54ACTQ
T
A
=
−55˚C to +125˚C
Guaranteed Limits
1.5
−1.2
Units
Conditions
5.0
5.0
V
V
(Notes 6, 7)
(Notes 6, 7)
Note 7:
Max number of outputs defined as (n). (n−1) Data Inputs are driven 0V to 3V, one output
@
GND.
Note 8:
Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f = 1 MHz.
AC Electrical Characteristics
V
CC
(V)
(Note 9)
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
Transparent Mode
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEBA, LEAB
to A
n
, B
n
Output Enable Time
OEBA or OEAB to A
n
or B
n
CEBA or CEAB to A
n
or B
n
Output Disable Time
OEBA or OEAB to A
n
or B
n
CEBA or CEAB to A
n
or B
n
Note 9:
Voltage Range 5.0 is 5.0V
±
0.5V
54ACTQ
T
A
= −55˚C
to +125˚C
C
L
= 50 pF
Max
9.5
ns
Units
Symbol
Parameter
Fig.
No.
5.0
2.0
Figure 4
Figure 4
5.0
2.0
11.0
ns
Figure 6
5.0
1.5
13.0
ns
Figure 6
5.0
1.5
9.0
ns
AC Operating Requirements
54ACTQ
T
A
= −55˚C
Symbol
Parameter
V
CC
(V)
(Note 10)
5.0
5.0
5.0
to +125˚C
C
L
= 50 pF
Guaranteed
Minimum
3.0
1.5
4.0
ns
ns
ns
Units
Fig.
No.
t
s
t
h
t
w
Setup Time, HIGH or LOW
A
n
or B
n
to LEBA or LEAB
Hold Time, HIGH or LOW
A
n
or B
n
to LEBA or LEAB
Latch Enable
Pulse Width, LOW
Figure 7
Figure 7
Figure 5
Note 10:
Voltage Range 5.0 is 5.0V
±
0.5V
5
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