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Intel 82804AA Memory Repeater
Hub for SDRAM (MRH-S)
Datasheet
®
November 1999
Order Number:
298024-001
Datasheet
82804AA MRH-S
R
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
82804AA Memory Repeater Hub for SDRAM (MRH-S) may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel. Implementations
of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM
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*Third-party brands and names are the property of their respective owners.
Copyright © Intel Corporation 1999
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Datasheet
82804AA MRH-S
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Contents
1.
Overview ...................................................................................................................................... 9
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
1.7.
1.8.
1.9.
2.
System Architecture ........................................................................................................ 9
Terminology..................................................................................................................... 9
Supported Memory Configurations................................................................................ 10
Maximum Memory Supported ....................................................................................... 11
System Interconnections ............................................................................................... 12
Direct RDRAM Channel Interface ................................................................................. 14
SDRAM Interface .......................................................................................................... 14
Clock Interface .............................................................................................................. 14
Register Interface .......................................................................................................... 14
Signal Description ...................................................................................................................... 15
2.1.
2.2.
2.3.
Direct RDRAM Channel Interface ................................................................................. 15
SDRAM Interface .......................................................................................................... 16
Miscellaneous Signals Interface.................................................................................... 17
2.3.1. Reset and Miscellaneous.................................................................................. 17
2.3.2. Reference Pins ................................................................................................. 17
MDID—Device ID Register............................................................................................ 19
MTR—Timing Register.................................................................................................. 19
MOR—Operation Register ............................................................................................ 21
MBSCRA—Memory Buffer Strength Control A Register............................................... 22
MBSCRB—Memory Buffer Strength Control B Register............................................... 23
EXCC—Direct RDRAM Current Register...................................................................... 23
RIR—RAC Initialization Register ................................................................................... 24
RAC Configuration Register A....................................................................................... 25
RAC Configuration Register B....................................................................................... 25
INIT—Initialization Register ........................................................................................... 25
VID—Vendor Identification Register.............................................................................. 27
RID—Revision Identification Register ........................................................................... 27
DID—Device Identification Register .............................................................................. 27
3.
Register Description................................................................................................................... 19
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
3.8.
3.9.
3.10.
3.11.
3.12.
3.13.
4.
Functional description ................................................................................................................ 29
4.1.
4.2.
Operation Overview....................................................................................................... 29
Protocol Overview ......................................................................................................... 29
4.2.1. Packet Format .................................................................................................. 29
4.2.2. SDRAM Command Truth Table........................................................................ 30
4.2.3. Current Calibration............................................................................................ 30
4.2.4. Temperature Calibration ................................................................................... 30
4.2.5. SDRAM CBR Refresh....................................................................................... 31
4.2.6. Self Refresh Entry and Exit............................................................................... 31
4.2.7. Registered DIMM Support ................................................................................ 31
4.2.8. SDRAM Command Issue Rules ....................................................................... 31
4.2.9. Write Operation Policy...................................................................................... 31
Datasheet
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82804AA MRH-S
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4.3.
4.2.10. ECC Support .....................................................................................................32
4.2.11. SDRAM Initialization..........................................................................................32
4.2.12. STR Support......................................................................................................32
4.2.13. System Clocking................................................................................................32
4.2.14. SDRAM Timing Parameters..............................................................................33
CMOS Signal Protocol ...................................................................................................33
4.3.1. Serial Control Packet Formats ..........................................................................34
4.3.2. Transactions......................................................................................................35
4.3.2.1. Reset...................................................................................................35
4.3.2.2. Register Operations ............................................................................36
MRH-S Ballout Assignment ...........................................................................................37
MRH-S Package Dimension ..........................................................................................42
RSL Normalized Trace Length Data ..............................................................................44
5.
Pinout and Package Information ................................................................................................37
5.1.
5.2.
5.3.
6.
Testability....................................................................................................................................47
6.1.
6.2.
Tri-state Mode................................................................................................................47
NAND Tree Test Mode ..................................................................................................47
6.2.1. SDRAM Interface Only ......................................................................................47
6.2.2. RAC Interface XOR Tree ..................................................................................50
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Datasheet
82804AA MRH-S
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Figures
Figure 1. 82840 Memory Subsystem using Two MRH-Ss ....................................................... 12
Figure 2. 82840 MCH Memory Subsystem using Four MRH-Ss ............................................. 13
Figure 3: Unbuffered SDRAM Block Diagram.......................................................................... 13
Figure 4. Connection of CMOS Signals ................................................................................... 33
Figure 5. Direct RDRAM Serial Control Packet Format for Register Read.............................. 34
Figure 6. Direct RDRAM Serial Control Packet Format for Register Write.............................. 34
Figure 7. Direct RDRAM Serial Control Packet Format for Non-Register Operation............... 34
Figure 8. SIO Reset Sequence ................................................................................................ 35
Figure 9. Register Read ........................................................................................................... 36
Figure 10. Register Write ......................................................................................................... 36
Figure 11. MRH-S Ballout (Top View—Left Side) .................................................................... 38
Figure 12. MRH-S Ballout (Top View—Right Side).................................................................. 39
Figure 13. Package Dimensions (241 BGA) – Top and Side Views ........................................ 42
Figure 14. Package Dimensions (241 BGA) – Bottom View.................................................... 43
Tables
Table 1. SDRAM Configurations .............................................................................................. 10
Table 2. Maximum Memory Support with DIMMs for Server/Workstation
Platforms (1–4 DIMMs).............................................................................................. 11
Table 3. Maximum Memory Support with DIMMs for Server/Workstation Platforms
(5–8 DIMMs) ............................................................................................................... 11
Table 4. Frequency Configurations .......................................................................................... 14
Table 5. SDRAM Command Truth Table................................................................................. 30
Table 6. Direct RDRAM Serial Packet Field Definitions........................................................... 35
Table 7. MRH-S Alphabetical Ballout List ................................................................................ 40
Table 8. BGA Package Dimensions (241 BGA)....................................................................... 43
Table 9. MRH-S RSL Normalized Trace Length Data ............................................................. 45
Table 10. NAND CHAIN #1...................................................................................................... 48
Table 11. NAND CHAIN #2...................................................................................................... 48
Table 12. NAND CHAIN #3...................................................................................................... 49
Table 13: RAC XOR Chain Mapping........................................................................................ 50
Datasheet
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