32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Features
SDRAM Unbuffered DIMM (UDIMM)
MT4LSDT464A – 32MB
MT4LSDT864A(I) – 64MB
MT4LSDT1664A(I) – 128MB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
•
•
•
•
•
•
•
•
•
•
•
168-pin, dual in-line memory module (DIMM)
PC100- and PC133-compliant
Unbuffered
32MB (4 Meg x 64)
2
, 64MB (8 Meg x 64),
128MB (16 Meg x 64)
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal SDRAM banks for hiding row access/
precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes CONCURRENT AUTO
PRECHARGE and auto refresh modes
Self refresh mode: 64ms, 4,096-cycle refresh
for 32MB and 64MB; 64ms, 8,192-cycle refresh
for 128MB
LVTTL-compatible inputs and outputs
Serial presence-detect (SPD)
Gold edge contacts
Figure 1:
168-Pin DIMM (MO-161)
Standard 25.4mm (1.0in)
Options
• Package
– 168-pin DIMM (standard)
– 168-pin DIMM (Pb-free)
• Operating temperature range
– Commercial (0°C to +65°C)
– Industrial (–40°C to +85°C)
1, 3
• Frequency/CAS Latency
– 7.5ns (133 MHz)/CL = 2
– 7.5ns (133 MHz)/CL = 3
– 8ns (100 MHz)/CL = 2
2
• PCB
– Standard 25.40mm (1.0in)
Marking
G
Y
None
I
-13E
-133
-10E
•
•
•
Notes: 1. Contact Micron for product availability.
2. Not recommended for new designs.
3. Industrial temperature option available in
-133 MHz only.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency
Industry
Nomenclature
PC133
PC133
PC100
Access Time
CL = 2
5.4ns
–
9ns
CL = 3
–
5.4ns
7.5ns
Setup Time
-13E
-133
-10E
Hold Time
133 MHz
133 MHz
100 MHz
Speed Grade
-13E
-133
-10E
2
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Features
Table 2:
Addressing
32MB
Refresh count
Device banks
Device configuration
Row addressing
Column addressing
Module ranks
4K
4 (BA0, BA1)
64Mb (4 Meg x 16)
4K (A0–A11)
256 (A0–A7)
1 (S0#, S2#)
64MB
4K
4 (BA0, BA1)
128Mb (8 Meg x 16)
4K (A0–A11)
512 (A0–A8)
1 (S0#, S2#)
128MB
8K
4 (BA0, BA1)
256Mb (16 Meg x 16)
8K (A0–A12)
512 (A0–A8)
1 (S0#, S2#)
Table 3:
Part Numbers and Timing Parameters
Module Density
32MB
32MB
32MB
32MB
32MB
32MB
64MB
64MB
64MB
64MB
64MB
64MB
64MB
64MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
Configuration
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
System Bus Speed
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
Part Number
3
MT4LSDT464AG-13E_
1
MT4LSDT464AY-13E_
2
MT4LSDT464AG-133_
2
MT4LSDT464AY-133_
2
MT4LSDT464AG-10E_
2
MT4LSDT464AY-10E_
1
MT4LSDT864AG-13E_
1
MT4LSDT864AY-13E_
MT4LSDT864AIG-133_
1
MT4LSDT864AG-133_
1
MT4LSDT864AIY-133_
1
MT4LSDT864AY-133_
MT4LSDT864AG-10E_
2
MT4LSDT864AY-10E_
1
MT4LSDT1664AG-13E_
MT4LSDT1664AY-13E_
MT4LSDT1664AIG-133_
1
MT4LSDT1664AG-133_
MT4LSDT1664AIY-133_
1
MT4LSDT1664AY-133_
MT4LSDT1664AG-10E_
2
MT4LSDT1664AY-10E_
2
Notes:
1. Contact Micron for product availability.
2. Not recommended for new designs.
3. The designators for component and PCB revision are the last two characters of each part
number. Consult factory for current revision codes. Example: MT4LSDT464AG-133G1
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4:
Pin Assignments
168-Pin DIMM Front
Pin Symbol Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
DNU
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
DNU
V
SS
NC
NC
V
DD
WE#
DQM0
DQM1
S0#
NC
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CK0
Notes:
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Symbol
V
SS
NC
S2#
DQM2
DQM3
NC
V
DD
NC
NC
DNU
DNU
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC
Pin
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
NC
SDA
SCL
V
DD
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
DNU
168-Pin DIMM Back
Pin Symbol Pin Symbol
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
DNU
V
SS
NC
NC
V
DD
CAS#
DQM4
DQM5
DNU
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
DNU
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
Symbol
V
SS
CKE0
DNU
DQM6
DQM7
DNU
V
DD
NC
NC
DNU
DNU
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
NC
Pin
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
DNU
NC
SA0
SA1
SA2
V
DD
126 NC/A12
1
147
1. Pin 126 is NC for 32MB and 64MB modules, or A12 for the 128MB module.
Figure 2:
Pin Locations (168-Pin DIMM)
Front View
U1
U2
U4
U5
U6
PIN 1
PIN 84
Back View
No components on this side of module
PIN 168
PIN 85
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pins may not correlate with symbols; refer to Table 4 on page 3 for more information
Pin Numbers
27, 111, 115
42, 79
Symbol
RAS#, CAS#,
WE#
CK0, CK2
Type
Input
Input
Description
Command inputs:
RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock:
CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Clock enable:
CKE activates (HIGH) and deactivates (LOW)
the CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle) or CLOCK SUSPEND OPERATION (burst access in progress).
CKE is synchronous except after the device enters power-down
and self refresh modes, where CKE becomes asynchronous
until after exiting the same mode. The input buffers, including
CK, are disabled during power-down and self refresh modes,
providing low standby power.
Chip select:
S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input/output mask:
DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank address:
BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address inputs:
Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial clock for presence-detect:
SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-detect address inputs:
These pins are used to
configure the presence-detect device.
Serial presence-detect data:
SDA is a bidirectional pin used
to transfer addresses and data into and out of the presence-
detect portion of the module.
Data I/Os:
Data bus.
128
CKE0
Input
30, 45
S0#, S2#
Input
28, 29, 46, 47, 112, 113,
130, 131
DQMB0–
DQMB7
Input
39, 122
BA0, BA1
Input
33–38, 117–121, 123,
126 (128MB)
A0–A11
(32MB, 64MB)
A0–A12
(128MB)
Input
83
165–167
82
SCL
SA0–SA2
SDA
Input
Input
Input/Output
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
74–77, 86–89, 91–95,
97–101, 103–104, 139–
142, 144, 149–151, 153–
156, 158–161
DQ0–DQ63
Input/Output
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions (Continued)
Pins may not correlate with symbols; refer to Table 4 on page 3 for more information
Pin Numbers
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110, 124,
133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
21, 22, 52, 53, 105, 106,
114, 125, 129, 132, 163
24, 25, 31, 44, 48, 50, 51,
61, 62, 63, 80, 81, 108,
109, 126 (32MB, 64MB),
134, 135, 145–147, 164
Symbol
V
DD
Type
Supply
Description
Power supply:
+3.3V ±0.3V.
V
SS
Supply
Ground.
DNU
NC
–
–
Do not use:
These pins are not used on these modules, but
are assigned pins on other modules in this product family.
Not connected:
These pins are not connected on these
modules.
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
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