54ACT573 Octal Latch with TRI-STATE Outputs
August 1998
54ACT573
Octal Latch with TRI-STATE
®
Outputs
General Description
The ’ACT573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output Enable
(OE) inputs.
The ’ACT573 is functionally identical to the ’ACT373 but has
inputs and outputs on opposite sides.
Features
n
I
CC
and I
OZ
reduced by 50%
n
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n
Useful as input or output port for microprocessors
n
Functionally identical to ’ACT373
n
TRI-STATE outputs for bus interfacing
n
Outputs source/sink 24 mA
n
’ACT573 has TTL-compatible inputs
n
Standard Military Drawing (SMD)
— ’ACT573: 5962-87664
Logic Symbols
IEEE/IEC
DS100332-1
DS100332-2
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Description
Latch Enable Input
TRI-STATE Output Enable Input
TRI-STATE Latch Outputs
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100332
www.national.com
Connection Diagrams
Pin Assignment for DIP
and Flatpak
Pin Assignment for LCC
DS100332-4
DS100332-3
www.national.com
2
Functional Description
The ’ACT573 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW the latches
store the information that was present on the D inputs a
setup time preceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are enabled. When OE
is HIGH the buffers are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Outputs
O
n
H
L
O
0
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH-to-LOW transition of Latch Enable
Logic Diagram
DS100332-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
= V
CC
+ 0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
= V
CC
+ 0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
Junction Temperature (T
J
)
CDIP
175˚C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
54ACT
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−55˚C to +125˚C
±
50 mA
±
50 mA
−65˚C to +150˚C
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
®
circuits outside databook specifications.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
V
CC
(V)
54ACT
T
A
=
−55˚C to +125˚C
Guaranteed
Limits
V
IH
Minimum High
Level Input
Voltage
Maximum Low
Level Input
Voltage
Minimum High
Level Output
Voltage
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
(Note 2)
V
IN
= V
IL
or V
IH
4.5
5.5
V
OL
Maximum Low
Level Output
Voltage
4.5
5.5
3.70
4.70
0.1
0.1
(Note 2)
V
IN
= V
IL
or V
IH
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
Maximum Input
Leakage Current
Maximum TRI-STATE
Leakage Current
Maximum
I
CC
/Input
(Note 3) Minimum
Dynamic Output
Current
5.5
5.5
50
−50
mA
mA
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
5.5
1.6
mA
5.5
5.5
0.50
0.50
V
µA
µA
I
OL
24 mA
24 mA
= V
CC
, GND
V
I
V
I
= V
IL
, V
IH
V
O
= V
CC
, GND
V
I
= V
CC
− 2.1V
V
V
I
OH
−24 mA
−24 mA
I
OUT
= 50 µA
V
or V
CC
− 0.1V
V
I
OUT
= −50 µA
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
OUT
= 0.1V
Units
Conditions
V
IL
V
OH
±
1.0
±
5.0
www.national.com
4
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
V
CC
(V)
(Continued)
54ACT
T
A
=
−55˚C to +125˚C
Guaranteed
Limits
Units
Conditions
I
CC
Maximum Quiescent
Supply Current
5.5
80.0
µA
V
IN
= V
CC
or GND
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
I
CC
for 54ACT
@
25˚C is identical to 74ACT
@
25˚C.
AC Electrical Characteristics
V
CC
Symbol
Parameter
(V)
(Note 5)
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
D
m
to O
n
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
1.5
1.5
1.5
1.5
11.5
11.0
13.5
10.5
ns
ns
ns
ns
5.0
1.5
12.0
ns
5.0
1.5
13.0
ns
5.0
1.5
13.5
ns
5.0
1.5
54ACT
T
A
= −55˚C
to +125˚C
C
L
= 50 pF
Min
Max
13.5
ns
Units
Fig.
No.
Note 5:
Voltage Range 5.0 is 5.0V
±
0.5V
AC Operating Requirements
V
CC
Symbol
Parameter
(V)
(Note 6)
54ACT
T
A
= −55˚C
to +125˚C
C
L
= 50 pF
Guaranteed
Minimum
t
s
t
h
t
w
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width, HIGH
5.0
5.0
ns
Note 6:
Voltage Range 5.0 is 5.0V
±
0.5V
Fig.
Units
No.
5.0
5.0
4.5
1.0
ns
ns
5
www.national.com
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
