7-bit programmable ‘A’ counter, latched and buffered Band 0 and
Band 1 outputs and the necessary control and latch circuitry for
accepting and latching the input data.
Data is presented serially under external control from a suitable
microprocessor. Although 30 bits of data are initially required to
program all counters, subsequent updating can be abbreviated to
19 bits, when only the ‘A’, ‘M’ and ‘B’ counters require changing.
The NJ88C25 is intended to be used in conjunction with a two-
modulus prescaler such as the SP8710 series to produce a
universal binary coded synthesiser.
PDA
PDB
F
V
LD
F
IN
V
SS
V
DD
BAND 0
OSC IN
1
2
3
4
18
17
16
15
CH
RB
MC
CAP
ENABLE
CLOCK
DATA
BAND 1
OSC OUT
5
NJ88C25
14
6
7
8
9
13
12
11
10
FEATURES
s
Low Power Consumption
DG18, DP18, MP18
Fig.1 Pin connections - top view
s
High Performance Sample and Hold Phase Detector
s
Serial Input with Fast Update Feature
ORDERING INFORMATION
NJ88C25 KA DG
Ceramic DIL Package
NJ88C25 KA DP
Plastic DIL Package
NJ88C25 KA MP
Miniature Plastic DIL Package
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
DD
2V
SS
:
20·5V
to 7V
Input voltage
Open drain output, pins 3 and 4:
7V
All other pins:
V
SS
20·3V
to V
DD
10·3V
Storage temperature:
265°C
to
1150°C
(DG package)
255°C
to
1125°C
(DP and MP packages)
RB
17
CAP
15
CH
18
OSC IN
OSC OUT
9
10
REFERENCE COUNTER
(11BITS)
42
f
r
SAMPLE/HOLD
PHASE
DETECTOR
1
PDA
LATCH 6 LATCH 7 LATCH 8
12
DATA 14
ENABLE
13
‘B’ REGISTER
FREQUENCY/
PHASE
DETECTOR
2
‘R’ REGISTER
f
V
PDB
CLOCK
‘M’ REGISTER
‘A’ REGISTER
4
V
SS
3
LOCK DETECT (LD)
LATCH 6
BAND 0
BAND 1
F
IN
8
11
5
LATCH 1 LATCH 2 LATCH 3
LATCH 4 LATCH 5
F
V
‘M’ COUNTER
(10 BITS)
‘A’ COUNTER
(7 BITS)
V
SS
CONTROL LOGIC
V
DD
V
SS
7
6
16
MODULUS
CONTROL
OUTPUT (MC)
Fig.2 Block diagram
NJ88C25
ELECTRICAL CHARACTERISTICS AT V
DD
= 5V
Test conditions unless otherwise stated:
V
DD
–V
SS
=2·7V to 5·5V. Temperature range = –30°C to +70°C
DC Characteristics
Value
Characteristic
Min.
Supply current
Typ.
5·5
0·7
3·7
Max.
mA
mA
mA
f
osc
, f
F
IN
= 20MHz
f
osc
, f
F
IN
= 1MHz
f
osc
, f
F
IN
= 10MHz
Units
Conditions
OUTPUTS
Modulus Control (MC), BAND 1 and BAND 2
High level
Low level
Lock Detect (LD) and F
V
Low level
Open drain pull-up voltage
PDB
High level
Low level
3-state leakage current
AC Characteristics
V
DD
20·4
0·4
0·4
7·0
4·6
0·4
±0·1
V
V
V
V
V
V
µA
I
SOURCE
= 1mA
I
SINK
= 1mA
I
SINK
= 4mA
I
SOURCE
= 4mA
I
SINK
= 4mA
Value
Characteristic
Min.
F
IN
and OSC IN input level
Max. operating frequency, f
F
IN
and f
osc
Propagation delay, clock to modulus control MC
Programming Inputs
Clock high time, t
CH
Clock low time, t
CL
Enable set-up time, t
ES
(see note 5)
Enable hold time, t
EH
Data set-up time, t
DS
Data hold time, t
DH
Clock rise and fall times
Positive threshold
Negative threshold
Phase Detector
Digital phase detector propagation delay
Gain programming resistor, RB
Hold capacitor, CH
Programming capacitor, CAP
Output resistance, PDA
200
20
30
0·5
0·5
0·2
0·2
0·2
0·2
0·2
3
50
Typ.
Max.
mV RMS 10MHz AC-coupled sinewave
MHz
Input squarewave V
DD
to V
SS
,
ns
See note 2
Units
Conditions
t
CH
2
500
5
1
1
5
ns
kΩ
nF
nF
kΩ
NOTES
1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs.
4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the OSC IN and
F
IN
inputs.
5. Clock to enable set-up time (t
ES
) is variable, dependent on f
OSC
. It needs to be specified in terms of f
OSC
, clock high time (t
CH
) and clock low time
(t
CL
) and must meet the following conditions: 431/f
OSC
<t
ES
,(t
CH
1t
CL
).
2
µs
µs
µs
µs
µs
µs
µs
V
V
All timing periods
are referenced to
the negative
transition of the
clock waveform.
See note 5
TTL compatible, see note 1
See note 3
0 to 5V
square
wave
NJ88C25
PIN DESCRIPTIONS
Pin no.
1
Name
PDA
Description
Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Voltage
increases as f
v
(the output from the ‘M’ counter) phase lead increases; voltage decreases as f
r
(the
output from the reference counter) phase lead increases. Output is linear over only a narrow phase
window, determined by gain (programmed by RB). In a type 2 loop, this pin is at (V
DD
2V
SS
)/2 when the
system is in lock.
Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.
f
v
.
f
r
or f
v
leading: positive pulses with respect to the bias point V
BIAS
f
v
,
f
r
or f
r
leading: negative pulses with respect to the bias point V
BIAS
f
v
= f
r
and phase error within PDA window: high impedance.
This pin is an open drain output from the ‘M’ counter.
An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.
The input to the main counters. It is normally driven from a prescaler, which may be AC-coupled or,
when a full logic swing is available, may be DC-coupled.
Negative supply (ground).
Positive supply (normally 5V)
2
PDB
3
4
5
6
7
9,10
F
V
LD
F
IN
V
SS
V
DD
OSC IN/ These pins form an on-chip reference oscillator when a series resonant crystal is connected across
OSC OUT them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. The addition of a 220Ω resistor between OSC OUT and
the crystal will improve stability. An external reference signal may, alternatively, be applied to OSC IN.
This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled.
The program range of the reference counter is 3 to 2047 , with the total division ratio being twice the
programmed number.
BAND 0/1
DATA
Two latch outputs, providing an output of the data from the ‘B’ register.
Information on this input is transferred to the internal data latches during the appropriate data read time
slot. DATA is high for a ‘1’ and low for a ‘0’. There are four data words which control the NJ88C25; MSB
is first in the order: ‘A’ (7 bits), ‘M’ (10 bits), ]B’ (2 bits) and ‘R’ (11 bits).
Data is clocked on the negative transition of the CLOCK waveform. If less than 30 negative clock
transitions have been received when the ENABLE line goes low (i.e., only ‘B’,‘M’ and ‘A’ will have been
clocked in), then the ‘R’ counter latch will remain unchanged and only ‘M’ and ‘A’ will be transferred from
the input shift register to the counter latches. This will protect the ‘R’ counter from being corrupted by
any glitches on the clock line after only ‘B’, ‘M’ and ‘A’ have been loaded. If 30 negative transitions have
been counted, then the ‘R’ counter will be loaded with the new data.
When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As soon as ENABLE is
high, the DATA and CLOCK inputs are enabled and data may be clocked into the device. The data is
transferred from the input shift register to the counter latches on the negative transition of the ENABLE
input and both inputs to the phase detector are synchronised to each other.
This pin allows an external capacitor to be connected in parallel with the internal ramp capacitor and
allows further programming of the device. (This capacitor is connected from CAP to V
SS
).
Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning
of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and
remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset.
This gives a total division ratio of
MP
1
A,
where
P
and
P
11
represent the dual-modulus prescaler
values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a
division ratio up to and including
4128/129.
The programming range of the ‘M’ counter is 8-1023
and, for correct operation,
M
>
A.
Where every possible channel is required, the minimum total division
ratio
N
should be:
N
>
P
2
2
P.
An external sample and hold phase comparator gain programming resistor should be connected
between this pin and V
SS
.
An external hold capacitor should be connected between this pin and V
SS
.
8, 11
12
13
CLOCK
14
ENABLE
15
16
CAP
MC
17
18
RB
CH
3
NJ88C25
2·0
V
DD
= 5V
OSC IN, F
IN
= 0V TO 5V SQUARE WAVE
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
1·5
8
7
6
5
4
3
2
TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO F
IN
AND OSC IN
1
2
3
4
5
6
7
INPUT FREQUENCY (MHz)
8
9
10
1
V
DD
= 5V
F
IN
= LOW FREQUENCY
0V TO 5V SQUARE WAVE
OSC IN
1·0
F
IN
0·5
10MHz
1MHz
0·2
0·4
0·6
0·8
1·0
1·2
INPUT LEVEL (V RMS)
1·4
1·6
Fig. 3 Typical supply current v. input frequency
Fig. 4 Typical supply current v. input level, OSC IN
PROGRAMMING
Reference Divider Chain
The comparison frequency depends upon the crystal
oscillator frequency and the division ratio of th ‘R’ counter,
which can be programmed in the range 3 to 2047, and a fixed
divide by two stage.
f
osc
R=
23fcomp
where
fosc
= oscillator frequency,
fcomp
= comparison frequency,
R
= ‘R’ counter ratio
For example, where the crystal frequency = 10MHz and a
channel spacing comparison frequency of 12·5kHz is required,
The division ratio
N
=
MP
1
A,
where
M
is the ratio of the ‘M’ counter in the range 8 to 1023
and
A
is the ratio of the ‘A’ counter in the range 0 to 127.
Note that
M
>
A
and
N
=
f
VCO
fcomp
For example, if the desired VCO frequency = 275MHz, the
comparison frequency is 12·5kHz and a two-modulus prescaler
of
464/65
is being used, then
6
N
= 275310
3
= 22310
3
12·5310
Now,
N
=
MP
1
A,
which can be rearranged as
N/P
=
M
1
A/P.
In our example we have
P
= 64, therefore
R=
10
7
= 400
2312·5310
3
Thus, the ‘R’ register would be programmed to 400 expressed
in binary. The total division ratio would then be 23400 = 800
since the total division ratio of the ‘R’ counter plus the
42
stage
is from 6 to 4094 in steps of 2.
VCO Divider Chain
The synthesised frequency of the voltage controlled oscillator
(VCO) will depend on the division ratios of the ‘M’ and ‘A’
counters, the ratio of the external two-modulus prescaler
(P/P
1
1)and
the comparison frequency .
A
22310
3
=
M
1
64
64
such that
M
= 343 and
A
/64 = 0·75.
Now,
M
is programmed to the integer part = 343 and
A
is
programmed to the fractional part364 i.e.,
A
= 0·75364 = 48.
NB
The minimum ratio
N
that can be used is
P
2
2
P
(=4032 in
our example) for all contiguous channels to be available.
To check:
N
= 343364148 = 22000, which is the required
division ratio and is greater than 4032 ( =
P
2
2
P
).
CLOCK
t
CH
t
CL
ENABLE
t
EH
t
ES
t
DS
t
EH
t
DH
t
ES
DATA
Fig. 5 Timing diagram showing timing periods required for correct operation
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