without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
1
IS61DDPB21M18A/A1/A2
IS61DDPB251236A/A1/A2
Package ballout and description
x36 FBGA Ball Configuration (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
CQ#
NC
NC
NC
NC
NC
NC
D
off
#
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
1
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
NC/SA
1
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R/W#
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
2
#
BW
3
#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
ODT
7
BW
1
#
BW
0
#
SA
VSS
VSS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD#
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
NC/SA
1
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
Notes:
1.
The following balls are reserved for higher densities: 3A for 36Mb, 10A for 72Mb, and 2A for 144Mb.
x18 FBGA Ball Configuration (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Notes:
1.
1
CQ#
NC
NC
NC
NC
NC
NC
D
off
#
NC
NC
NC
NC
NC
NC
TDO
2
1
NC/SA
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/W#
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
1
#
NC/SA
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
1
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
ODT
7
NC/SA
1
BW
0
#
SA
VSS
VSS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD#
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
NC/SA
1
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
The following balls are reserved for higher densities: 10A for 36Mb, 2A for 72Mb, 7A for 144Mb, and 5B for 288Mb.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
2
IS61DDPB21M18A/A1/A2
IS61DDPB251236A/A1/A2
Ball Descriptions
Symbol
K, K#
Type
Input
Description
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
These balls cannot remain VREF level.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals are free running clocks and
do not stop when Q tri-states.
DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock
time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz.
Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ#.
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. These inputs are ignored when device is deselected.
Data input and output signals. Input data must meet setup and hold times around the rising edges of
K and K# during WRITE operations. These pins drive out the requested data when the read
operation is active. Valid output data is synchronized to the respective CQ and CQ#.
See BALL CONFIGURATION figures for ball site location of individual signals.
The x18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin.
The x36 device uses DQ0~DQ35.
Synchronous Read or Write input. When LD# is low, this input designates the access type (read
when it is High, write when it is Low) for loaded address. R/W# must meet the setup and hold times
around edge of K.
Synchronous load. This input is brought Low when a bus cycle sequence is defined. This definition
includes address and read/write direction.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals are sampled on the same edge as the corresponding
data and must meet setup and hold times around the rising edges of K and #K for each of the two
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating
Conditions for range.
Ground of the device
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this ball
to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance
mode. This ball cannot be connected directly to VSS or left unconnected.
In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ.
The ODT range is selected by ODT control input.
IEEE 1149.1 input pins for JTAG
IEEE 1149.1 output pins for JTAG
No connect: These signals should be left floating or connected to ground to improve package heat
dissipation.
ODT control; Refer to SRAM features for the details.
CQ, CQ#
Output
Doff#
QVLD
SA
Input
Output
Input
DQ0 - DQn
Bidir
R/W#
LD#
BW
x
#
V
REF
V
DD
V
DDQ
V
SS
Input
Input
Input
Input
reference
Power
Power
Ground
ZQ
Input
TMS, TDI, TCK
TDO
NC
ODT
Input
Output
N/A
Input
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
3
IS61DDPB21M18A/A1/A2
IS61DDPB251236A/A1/A2
SRAM Features description
Block Diagram
36(18)
Data
Register
Burst2
36x2(18x2)
Write
Driver
36x2 (18x2)
36 (18)
DQ(Data-out
&Data-In)
Address Decoder
Sense Amplifiers
512K x 36
(1M x 18)
Memory Array
Output
Reg
LD#
R/W#
BW
x
#
4 (2)
Control
Logic
Output Select
Addresses
18 (19)
Add Reg &
Burst
Control
18 (19)
36x2
(18x2)
72
(36)
36
(18)
Input/Output Driver
CQ, CQ#
(Echo Clocks)
K
K#
Clock
Generator
Select Output Control
/D
off
Note: Numerical values in parentheses refer to the x18 device configuration
.
Read Operations
The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R/W# in active high
state at the rising edge of the K clock. K and K#, are also used to control the timing to the outputs. The data
corresponding to the first address is clocked two and half cycles later by the rising edge of the K# clock. The data
corresponding to the second burst is clocked three cycles later by the following rising edge of the K clock. A set of free-
running echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs. The echo clocks can
be used as data capture clocks by the receiver device.
Whenever LD# is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD# is high)
does not terminate the previous read. The output drivers disable automatically to a high-Z state.
Write Operations
Write operations can also be initiated at every other rising edge of the K clock whenever R/W# is low. The write
address is also registered at that time. When the address needs to change, LD# needs to be low simultaneously to be
registered by the rising edge of K. Again, the write always occurs in bursts of two.
Because of its common I/O architecture, the data bus must be tri-stated at least one cycle before the new data-in is
presented at the DQ bus.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
4
IS61DDPB21M18A/A1/A2
IS61DDPB251236A/A1/A2
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is
presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write
burst address follows next, registered by the rising edge of K#.
The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into
the array on the third write cycle. A read cycle to the last two write address produces data from the write buffers.
Similarly, a read address followed by the same write address produces the latest write data. The SRAM maintains data
coherency.
During a write, the byte writes independently control which byte of any of the two burst addresses is written. (See
X18/X36 Write Truth Tables
and
Timing Reference Diagram for Truth Table)
Whenever a write is disabled (R/W# is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS
to enable the SRAM to adjust
its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the
SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee
impedance matching is between 175Ω and 350Ω at V
DDQ
=1.5V. The RQ resistor should be placed less than two inches
away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.
The ZQ pin can also be directly connected to V
DDQ
to obtain a minimum impedance setting. ZQ should not be
connected to V
SS
.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in
supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances
values. The final impedance value is achieved within 1024clock cycles.
Valid Data Indicator (QVLD)
A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with
the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle
before the final valid read data arrives.
Delay Locked Loop (DLL)
Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to
enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match
the clock frequency. Therefore device can have stable output over the temperature and voltage variation.
DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the
AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL
off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or old QUAD
mode.
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being
reset, it gets locked after 2048 cycles of stable clock.
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