LT1611
Inverting 1.4MHz Switching
Regulator in SOT-23
FEATURES
s
s
s
s
s
s
s
s
s
s
DESCRIPTIO
Very Low Noise: 1mV
P–P
Output Ripple
– 5V at 150mA from a 5V Input
Better Regulation Than a Charge Pump
Effective Output Impedance: 0.14Ω
Uses Tiny Capacitors and Inductors
Internally Compensated
Fixed Frequency 1.4MHz Operation
Low Shutdown Current: <1µA
Low V
CESAT
Switch: 300mV at 300mA
Tiny 5-Lead SOT-23 Package
The LT
®
1611 is the industry’s first inverting 5-lead SOT-23
current mode DC/DC converter. Intended for use in small,
low power applications, it operates from an input voltage
as low as 1.1V and switches at 1.4MHz, allowing the use
of tiny, low cost capacitors and inductors 2mm or less in
height. Its small size and high switching frequency enable
the complete DC/DC converter function to consume less
than 0.25 square inches of PC board area. Capable of
generating – 5V at 150mA from a 5V supply or – 5V at
100mA from a 3V supply, the LT1611 replaces nonregulated
“charge pump” solutions in many applications.
The LT1611 operates in a dual inductor inverting topology
which filters the input side as well as the output side of the
DC/DC converter. Fixed frequency switching ensures a
clean output free from low frequency noise typically present
with charge pump solutions. No load quiescent current of
the LT1611 is 3mA, while in shutdown quiescent current
drops to 0.5µA. The 36V switch allows V
IN
to V
OUT
differential of up to 33V.
The LT1611 is available in the 5-lead SOT-23 package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s
s
s
s
s
MR Head Bias
Digital Camera CCD Bias
LCD Bias
GaAs FET Bias
Positive-to-Negative Conversion
TYPICAL APPLICATIO
V
IN
5V
V
IN
L1A
22µH
C2
1µF
L1B
22µH
D1
SW
LT1611
NFB
GND
R2
10k
R1
29.4k
1200pF
SHDN
C1
22µF
+
V
OUT
–5V
150mA
C3
22µF
V
OUT
20mV/DIV
AC COUPLED
LOAD CURRENT
C1: AVX TAJB226M010
C2: TAIYO YUDEN LMK212BJ105MG
C3: TAIYO YUDEN JMK325BJ226MM (1210 SIZE)
D1: MBR0520
L1: SUMIDA CLS62-220 OR 2× MURATA LQH3C220 (UNCOUPLED)
1611 TA01
150mA
50mA
100µs/DIV
1611 F10
Figure 1. 5V to – 5V, 150mA Low Noise Inverting DC/DC Converter
U
Transient Response
U
U
1
LT1611
ABSOLUTE
MAXIMUM
RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW
SW 1
GND 2
NFB 3
4 SHDN
5 V
IN
V
IN
Voltage .............................................................. 10V
SW Voltage ................................................– 0.4V to 36V
NFB Voltage ............................................................. – 3V
Current into NFB Pin .............................................
±1mA
SHDN Voltage .......................................................... 10V
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
Commercial ............................................. 0°C to 70°C
Extended Commercial (Note 2) ........... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LT1611CS5
S5 PART MARKING
LTES
S5 PACKAGE
5-LEAD PLASTIC SOT-23
T
JMAX
= 125°C,
θ
JA
= 256°C/W
Consult factory for Industrial and Military grade parts.
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
IN
= 1.5V, V
SHDN
= V
IN
unless otherwise noted.
PARAMETER
Minimum Operating Voltage
Maximum Operating Voltage
NFB Pin Bias Current
Feedback Voltage
Quiescent Current
Quiescent Current in Shutdown
Reference Line Regulation
Switching Frequency
Maximum Duty Cycle
Switch Current Limit
Switch V
CESAT
Switch Leakage Current
SHDN Input Voltage High
SHDN Input Voltage Low
SHDN Pin Bias Current
V
SHDN
= 3V
V
SHDN
= 0V
25
0
(Note 3)
I
SW
= 300mA
V
SW
= 5V
1
0.3
50
0.1
V
SHDN
= 1.5V, Not Switching
V
SHDN
= 0V, V
IN
= 2V
V
SHDN
= 0V, V
IN
= 5V
1.5V
≤
V
IN
≤
10V
q
q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN
TYP
0.9
MAX
1.1
10
– 6.7
– 1.255
4.5
0.5
1.0
0.2
1.8
UNITS
V
V
µA
V
mA
µA
µA
%/V
MHz
%
mA
V
NFB
= –1.23V
q
q
– 2.7
– 1.205
– 4.7
– 1.23
3
0.01
0.01
0.02
1.0
82
550
1.4
86
800
300
0.01
350
1
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
C grade device specifications are guaranteed over the 0°C to 70°C
temperature range. In addition, C grade device specifications are assured
over the – 40°C to 85°C temperature range by design or correlation, but
are not production tested.
Note 3:
Current limit guaranteed by design and/or correlation to static test.
Slope compensation reduces current limit at higher duty cycle.
2
U
W
U
U
W W
W
mV
µA
V
V
µA
µA
LT1611
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency, V
OUT
= – 5V
85
80
75
EFFICIENCY (%)
70
65
60
55
50
0
25
50
75
100
LOAD CURRENT (mA)
125
150
1611 G01
V
IN
= 5V
–1.235
NFB PIN BIAS CURRENT (µA)
–25
0
25
50
TEMPERATURE (°C)
75
100
1611 G02
V
NFB
(V)
V
IN
= 3V
Switch V
CESAT
vs Switch Current
700
600
500
T
A
= 25°C
SHDN PIN BIAS CURRENT (µA)
40
50
SWITCH CURRENT LIMIT (mA)
V
CESAT
(mV)
400
300
200
100
0
0
100
200 300 400 500
SWITCH CURRENT (mA)
600
700
Oscillator Frequency vs
Temperature
2.00
1.75
V
IN
= 5V
OPERATING CURRENT (mA)
6.0
5.5
SWITCHING FREQUENCY (MHz)
SWITCH CURRENT LIMIT (mA)
1.50
1.25
1.00
0.75
0.50
0.25
0
–50
V
IN
= 1.5V
–25
0
25
50
TEMPERATURE (°C)
* Includes bias current through R1, R2 and Schottky leakage current at T
≥
75°C
U W
1611 G04
V
NFB
vs Temperature
–1.245
–1.240
6
5
4
3
2
1
NFB Pin Bias Current vs
Temperature
–1.230
–1.225
–1.220
–1.215
–1.210
–50
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1611 G03
SHDN Pin Bias Current vs V
SHDN
900
800
700
600
500
400
300
200
100
Switch Current Limit vs Duty Cycle
T
A
= 25°C
30
20
10
0
0
1
2
3
4
SHDN PIN VOLTAGE (V)
5
1611 G05
0
10
20
30
40
50
60
DUTY CYCLE (%)
70
80
1611 G06
No-Load Operating Quiescent
Current vs Temperature*
900
800
700
600
500
400
300
200
100
Switch Current Limit vs
Temperature (Duty Cycle = 30%)
5.0
4.5
4.0
3.5
3.0
2.5
75
100
1611 G07
2.0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1611 G08
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1611 G09
3
LT1611
PIN FUNCTIONS
SW (Pin 1):
Switch Pin. Minimize trace area at this pin to
keep EMI down.
GND (Pin 2):
Ground. Tie directly to local ground plane.
NFB (Pin 3):
Negative Feedback Pin. Minimize trace area.
Reference voltage is –1.23V. Connect resistive divider tap
here. The suggested value for R2 is 10k. Set R1 and R2
according to:
1
.
23
+
4
.
5
•
10
−
6
R2
SHDN (Pin 4):
Shutdown Pin. Tie to 1V or more to enable
device. Ground to shut the device down.
R1
=
V
OUT
−
1
.
23
BLOCK DIAGRAM
V
IN
5
R5
40k
–
Q1
V
OUT
R1
(EXTERNAL)
NFB
R2
(EXTERNAL)
Q2
x10
R3
30k
R4
140k
3 NFB
C
C
A=3
1.4MHz
OSCILLATOR
SHDN
4
SHUTDOWN
C
PL
(OPTIONAL)
Figure 2
OPERATIO
The LT1611 combines a current mode, fixed frequency
PWM architecture with a –1.23V reference to directly
regulate negative outputs. Operation can be best under-
stood by referring to the block diagram of Figure 2. Q1 and
Q2 form a bandgap reference core whose loop is closed
around the output of the converter. The driven reference
point is the lower end of resistor R4, which normally sits
at a voltage of –1.23V. As the load current changes, the
NFB pin voltage also changes slightly, driving the output
of g
m
amplifier A1. Switch current is regulated directly on
a cycle-to-cycle basis by A1’s output. The flip-flop is set at
the beginning of each cycle, turning on the switch. When
the summation of a signal representing switch current and
a ramp generator (introduced to avoid subharmonic oscil-
lations at duty factors greater than 50%) exceeds the V
C
signal, comparator A2 changes stage, resetting the flip-
flop and turning off the switch. Output voltage decreases
(the magnitude increases) as switch current is increased.
The output, attenuated by external resistor divider R1 and
R2, appears at the NFB pin, closing the overall loop.
Frequency compensation is provided internally by R
C
and
C
C
. Transient response can be optimized by the addition of
a phase lead capacitor, C
PL
, in parallel with R1 in applica-
tions where large value or low ESR output capacitors are
used.
As load current is decreased, the switch turns on for a
shorter period each cycle. If the load current is further
decreased, the converter will skip cycles to maintain
output voltage regulation.
The LT1611 can work in either of two topologies. The
simpler topology appends a capacitive level shift to a
4
+
R
C
RAMP
GENERATOR
Σ
–
W
U
U
U
U
V
IN
(Pin 5):
Input Supply Pin. Must be locally bypassed.
V
IN
R6
40k
1 SW
COMPARATOR
A1
g
m
FF
S
DRIVER
Q
Q3
+
A2
R
+
0.15Ω
–
2 GND
1611 BD
LT1611
OPERATIO
boost converter, generating a negative output voltage,
which is directly regulated. The circuit schematic is de-
tailed in Figure 3. Only one inductor is required, and the
two diodes can be in a single SOT-23 package. Output
noise is the same as in a boost converter, because current
is delivered to the output only during the time when the
LT1611’s internal switch is off.
If D2 is replaced by an inductor, as shown in Figure 4, a
higher performance solution results. This converter topol-
ogy was developed by Professor S. Cuk of the California
Institute of Technology in the 1970s. A low ripple voltage
results with this topology due to inductor L2 in series with
the output. Abrupt changes in output capacitor current are
eliminated because the output inductor delivers current to
the output during both the off-time and the on-time of the
LT1611 switch. With proper layout and high quality output
capacitors, output ripple can be as low as 1mV
P–P
.
The operation of Cuk’s topology is shown in Figures 5
and 6. During the first switching phase, the LT1611’s
switch, represented by Q1, is on. There are two current
loops in operation. The first loop begins at input capacitor
C1, flows through L1, Q1 and back to C1. The second loop
flows from output capacitor C3, through L2, C2, Q1 and
back to C3. The output current from R
LOAD
is supplied by
L2 and C3. The voltage at node SW is V
CESAT
and at node
SWX the voltage is –(V
IN
+ |V
OUT
|). Q1 must conduct both
L1 and L2 current. C2 functions as a voltage level shifter,
with an approximately constant voltage of (V
IN
+ |V
OUT
|)
across it.
C2
1µF
D2
V
IN
+
C1
SHUTDOWN
GND
R2
10k
GND
R2
10k
1611 F03
Figure 3. Direct Regulation of Negative Output
Using Boost Converter with Charge Pump
Figure 4. L2 Replaces D2 to Make Low Output Ripple
Inverting Topology. Coupled or Uncoupled Inductors Can
Be Used. Follow Phasing If Coupled for Best Results
+
+
U
When Q1 turns off during the second phase of switching,
the SW node voltage abruptly increases to (V
IN
+ |V
OUT
|).
The SWX node voltage increases to V
D
(about 350mV).
Now current in the first loop, begining at C1, flows through
L1, C2, D1 and back to C1. Current in the second loop flows
from C3 through L2, D1 and back to C3. Load current
continues to be supplied by L2 and C3.
An important layout issue arises due to the chopped
nature of the currents flowing in Q1 and D1. If they are both
tied directly to the ground plane before being combined,
switching noise will be introduced into the ground plane.
It is almost impossible to get rid of this noise, once present
in the ground plane. The solution is to tie D1’s cathode to
the ground pin of the LT1611 before the combined cur-
rents are dumped into the ground plane as drawn in
Figures 4, 5 and 6. This single layout technique can
virtually eliminate high frequency “spike” noise so often
present on switching regulator outputs.
Output ripple voltage appears as a triangular waveform
riding on V
OUT
. Ripple magnitude equals the ripple current
of L2 multiplied by the equivalent series resistance (ESR)
of output capacitor C3. Increasing the inductance of L1
and L2 lowers the ripple current, which leads to lower
output voltage ripple. Decreasing the ESR of C3, by using
ceramic or other low ESR type capacitors, lowers output
ripple voltage. Output ripple voltage can be reduced to
arbitrarily low levels by using large value inductors and
low ESR, high value capacitors.
L1
L1
V
IN
D1
V
IN
LT1611
SHDN
NFB
SW
–V
OUT
R1
C3
C2
1µF
L2
+
C1
D1
V
IN
LT1611
NFB
SW
–V
OUT
R1
C3
1611 F04
5
FPGA/CPLD
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