XC61G
Series
Low Voltage Detectors (V
DF
= 0.8V½1.5V)
Standard Voltage Detectors (V
DF
1.6V½6.0V)
ETR0203_003
■GENERAL
DESCRIPTION
The XC61G series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser
trimming technologies.
Detect voltage is extremely accurate with minimal temperature drift.
Both CMOS and N-channel open drain output
configurations are available.
■APPLICATIONS
●Microprocessor
reset circuitry
●Memory
battery back-up circuits
●Power-on
reset circuits
●Power
failure detection
●System
battery life and charge voltage monitors
■FEATURES
Highly Accurate
:
±2%
Low Power Consumption
: 0.7
μA
[ V
IN
=1.5V ] (TYP.)
Detect Voltage Range
: 0.8V ~ 1.5V in 0.1V
increments (Low Voltage)
: 1.6V½6.0V in 0.1V
increments (Standard Voltage)
Operating Voltage Range
: 0.7V ~ 6.0V (Low Voltage)
: 0.7V½10.0V (Standard Voltage)
Detect Voltage Temperature characteristics
:
±100ppm/℃
(TYP.)
Output Configuration
: N-channel open drain or CMOS
CMOS
Package
: USP-3
Environmentally Friendly:
EU RoHS Compliant, Pb Free
■TYPICAL
APPLICATION CIRCUITS
■TYPICAL
PERFORMANCE CHARACTERISTICS
1/16
XC61G
Series
■OPERATIONAL
EXPLANATION
●CMOS
output
①
When input voltage (V
IN
) rises above detect voltage (V
DF
), output voltage (V
OUT
) will be equal to V
IN
.
(A condition of high impedance exists with N-ch open drain output configurations.)
②
When input voltage (V
IN
) falls below detect voltage (V
DF
), output voltage (V
OUT
) will be equal to the ground voltage
(V
SS
) level.
③
When input voltage (V
IN
) falls to a level below that of the minimum operating voltage (V
MIN
), output will become
unstable. In this condition, V
IN
will equal the pulled-up output (should output be pulled-up.)
④
When input voltage (V
IN
) rises above the ground voltage (V
SS
) level, output will be unstable at levels below the
minimum operating voltage (V
MIN
). Between the V
MIN
and detect release voltage (V
DR
) levels, the ground voltage (V
SS
)
level will be maintained.
⑤
When input voltage (V
IN
) rises above detect release voltage (V
DR
), output voltage (V
OUT
) will be equal to V
IN
.
(A condition of high impedance exists with N-ch open drain output configurations.)
⑥
The difference between V
DR
and V
DF
represents the hysteresis range.
●Timing
Chart
4/16
XC61G
Series
■NOTES
ON USE
1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent
damage to the device.
2. When a resistor is connected between the V
IN
pin and the input with CMOS output configurations, oscillation may occur
as a result of voltage drops at R
IN
if load current (I
OUT
) exists. (refer to the Oscillation Description (1) below)
3. When a resistor is connected between the V
IN
pin and the input with CMOS output configurations, irrespective of N-ch
output configurations, oscillation may occur as a result of through current at the time of voltage release even if load
current (I
OUT
) does not exist. (refer to the Oscillation Description (2) below )
4. With a resistor connected between the V
IN
pin and the input, detect and release voltage will rise as a result of the IC's
supply current flowing through the V
IN
pin.
5. In order to stabilize the IC's operations, please ensure that V
IN
pin's input frequency's rise and fall times are more than
severalμs / V.
6. Please use N-ch open drains configuration, when a resistor R
IN
is connected between the V
IN
pin and power source.
In such cases, please ensure that R
IN
is less than 10kΩ and that C is more than 0.1μF.
●Oscillation
Description
(1) Output current oscillation with the CMOS output configuration
When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load
current (I
OUT
) will flow at R
L
. Because a voltage drop (R
IN
x I
OUT
) is produced at the R
IN
resistor, located between the
input (IN) and the V
IN
pin, the load current will flow via the IC's V
IN
pin. The voltage drop will also lead to a fall in the
voltage level at the V
IN
pin. When the V
IN
pin voltage level falls below the detect voltage level, detect operations will
commence. Following detect operations, load current flow will cease and since voltage drop at R
IN
will disappear, the
voltage level at the V
IN
pin will rise and release operations will begin over again.
Oscillation may occur with this "release - detect - release" repetition.
Further, this condition will also appear via means of a similar mechanism during detect operations.
(2) Oscillation as a result of through current
Since the XC61G series are CMOS IC
S
, through current will flow when the IC's internal circuit switching operates (during
release and detect operations). Consequently, oscillation is liable to occur as a result of drops in voltage at the through
current's resistor (R
IN
) during release voltage operations. (refer to Figure 3 )
Since hysteresis exists during detect operations, oscillation is unlikely to occur.
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