A3930
and
A3931
Automotive 3-Phase BLDC Controller and MOSFET Driver
FEATURES AND BENEFITS
▪ igh current three-phase gate drive for N-channel
H
MOSFETs
▪ ynchronous rectification
S
▪ ross-conduction protection
C
▪ harge pump and top-off charge pump for 100% PWM
C
▪ ntegrated commutation decoder logic
I
▪ peration over 5.5 to 50 V supply voltage range
O
▪ xtensive diagnostics output
E
▪ rovides +5 V Hall sensor power
P
▪ ow-current sleep mode
L
The A3930 and A3931 are three-phase brushless DC (BLDC)
motor controllers for use with N-channel external power
MOSFETs. They incorporate much of the circuitry required
to design a cost-effective three-phase motor drive system, and
have been specifically designed for automotive applications.
A key automotive requirement is functionality over a wide
input supply range. A unique charge pump regulator pro-
vides adequate (>10 V) gate drive for battery voltages down
to 7 V, and allows the device to operate with a reduced gate
drive at battery voltages down to 5.5 V. Power dissipation in
the charge pump is minimized by switching from a voltage
doubling mode at low supply voltage to a dropout mode at
the nominal running voltage of 14 V.
A bootstrap capacitor is used to provide the above-battery
supply voltage required for N-channel MOSFETs. An
internal charge pump for the high-side drive allows for DC
(100% duty cycle) operation.
Internal fixed-frequency PWM current control circuitry can
be used to regulate the maximum load current. The peak
load current limit is set by the selection of an input reference
voltage and external sensing resistor. The PWM frequency
is set by a user-selected external RC timing network. For
added flexibility, the PWM input can be used to provide
Continued on the next page…
DESCRIPTION
PACKAGE:
48-Lead LQFP with exposed thermal pad
(suffix JP)
Not to scale
Typical Application
3930-DS Rev. 5
MCO-0000483
July 27, 2018
A3930
and
A3931
DESCRIPTION (CONTINUED)
Automotive 3-Phase BLDC Controller
and MOSFET Driver
speed and torque control, allowing the internal current control
circuit to set the maximum current limit.
Efficiency is enhanced by using synchronous rectification. The
power FETs are protected from shoot-through by integrated
crossover control with dead time. The dead time can be set by a
single external resistor.
The A3930 and A3931 only differ in their response to the all-zero
combination on the Hall inputs. In this state, the A3930 indicates
a logic fault, but the A3931 pre-positions the motor in an unstable
starting position suitable for start-up algorithms in microproces-
sor-driven “sensor-less” control systems.
Both devices are supplied in a 48-pin LQFP with exposed thermal
pad. This is a small footprint (81 mm
2
) power package. The pack-
age is lead (Pb) free, with 100% matte-tin leadframe plating.
SELECTION GUIDE
Part Number
A3930KJPTR-T
A3931KJPTR-T
* Contact Marketing
Option
Hall short detection
Pre-positioning
Packing
1500 pieces/reel
1500 pieces/reel
Terminals
48
48
Package
LQFP surface mount
LQFP surface mount
ABSOLUTE MAXIMUM RATINGS
Parameter
Load Supply Voltage
Logic Input/Output Voltage
Symbol
V
BB
V
RESET
V
GHx
V
GLx
V
Cx
Output Voltage Range
V
Sx
VBB pin
RESET pin input
Remaining logic pins
GHA, GHB, and GHC pins
GLA, GLB, and GLC pins
CA, CB, and CC pins
SA, SB, and SC pins
CSP, CSN, and LSS pins
CSO, VDSTH pins
VDRAIN pin
Operating Temperature Range (K)
Junction Temperature
Transient Junction Temperature
Storage Temperature Range
ESD Rating, Human Body Model
ESD Rating, Charged Device Model
T
A
T
J
T
tJ
T
S
AEC-Q100-002, all pins except CP1
AEC-Q100-002, pin CP1
AEC-Q100-011, all pins
Overtemperature event not exceed-
ing 1 s, lifetime duration not exceed-
ing 10 hr; guaranteed by design
characterization
Conditions
Rating
–0.3 to 50
–0.3 to 6
–0.3 to 7
V
Sx
to V
Sx
+ 15
–5 to 16
V
Sx
+ 15
–5 to 55
–4 to 6.5
–0.3 to 6.5
–0.3 to 55
–40 to 150
150
175
–55 to 150
2000
1000
1050
Units
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
°C
V
V
V
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
A3930
and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
FUNCTIONAL BLOCK DIAGRAM
VBAT+
CP
VBB
V5BD
V5
CV5
VDRAIN
MODE
Phase A of three phases
COAST
BRAKE
Boostrap
Monitor
High-Side
Drive
GHA
RGHA
ΦB
Charge
Pump
CA
CBOOTA
H1
H2
H3
See Note 1
ΦC
V5
+5V Ref
CP2
CP1
P
QV5
Charge
Pump
Regulator
VREG
CREG
RESET
DIR
H1
Control
Logic
SA
H2
ΦA
H3
VREG
Low-Side
Drive
GLA
RGLA
LSS
RDEAD
PWM
TACHO
R
DIRO
Q
S
ESF
Diagnostics and
Protection
–UVLO
–TSD
–Short to Supply
–Short to Ground
–Shorted Winding
–Low Load
Pad
Blanking
TEST
OSC
FF1
CSP
CSN
RSENSE
FF2
VDSTH
RT
RC
CT
REF
CSOUT
AGND
P
Note 1:
Allegro-recommended automotive-qualified Hall latches:
APS122x5
and
APS122x0.
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
A3930
and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
ELECTRICAL CHARACTERISTICS:
at T
J
= –40°C to 150°C, V
BB
= 7 to 45 V, unless otherwise noted
[1]
Characteristics
SUPPLY AND REFERENCE
VBB Functional Operating Range
[6]
VBB Quiescent Current
V5 Quiescent Current
V
BB
I
BBQ
I
BBS
I
V5Q
Function correct, parameters not guaranteed
RESET = High, outputs = Low
RESET = Low, sleep mode
RESET = High, outputs = Low
V
BB
≥ 7.4 V,
I
REG
= 0 to 15 mA
VREG Output Voltage
V
REG
6 V < V
BB
< 7.4 V
I
REG
= 0 to 15 mA
5.5 V < V
BB
< 6 V,
I
REG
< 10 mA
Bootstrap Diode Forward Voltage
Bootstrap Diode Resistance
Bootstrap Diode Current Limit
Top-off Charge Pump Current Limit
High-Side Gate Drive Static Load Resistance
V5 Output Voltage
V
BE
of External Transistor QV5
V5BD Base Drive Capability for QV5
[2]
GATE OUTPUT DRIVE
Turn-On Rise Time
Turn-Off Fall Time
Pull-Up On Resistance
Pull-Down On Resistance
Short-Circuit Current – Source
[2]
Short-Circuit Current – Sink
GHx Output Voltage
GLx Output Voltage
Turn-Off Propagation Delay
t
r
t
f
R
DS(on)UP
R
DS(on)DN
I
SC(source)
I
SC(sink)
V
GHx
V
GLx
t
p(off)
From Hall input change to unloaded gate
output change
From other control input change to
unloaded gate output change
R
DEAD
= 5 kΩ
Dead Time (turn-off to turn-on delay)
t
DEAD
R
DEAD
= 50 kΩ
R
DEAD
= 400 kΩ
RDEAD = tied to V5
C
LOAD
= 3300 pF, 20% to 80% points
C
LOAD
= 3300 pF, 80% to 20% points
T
J
= 25°C,
I
GHx
= –150 mA
T
J
= 150°C,
I
GHx
= –150 mA
T
J
= 25°C,
I
GLx
= 150 mA
T
J
= 150°C,
I
GLx
= 150 mA
T
J
= 25°C
T
J
= 25°C
t
w
< 10 µs
Bootstrap capacitor fully charged
–
–
3
4.6
1
1.5
–
–
V
Cx
– 0.2
V
REG
– 0.2
300
–
–
835
–
–
60
40
4
5.6
1.5
2.3
–500
850
–
–
500
150
180
960
3.3
6
–
–
5
6.6
2
3
–
–
–
–
700
200
–
1090
–
–
ns
ns
Ω
Ω
Ω
Ω
mA
mA
V
V
ns
ns
ns
ns
µs
µs
V
fBOOT
r
D
I
DBOOT
I
TOCPM
R
GSH
V
5
V
BEEXT
I
5BD
I
D
= 10 mA
I
D
= 100 mA
r
D(100 mA)
= (V
fBOOT(150 mA)
–
V
fBOOT(50 mA)
) / 100 mA
5.5
–
–
–
12.10
2 × V
BB
–2.7
9
0.4
1.5
6
250
–
250
4.75
–
–
–
11
–
–
13
–
10
0.7
2.2
10
500
200
–
5
–
–
50
14
10
5
13.75
–
–
1.0
2.8
20
750
–
–
5.25
1
–2
V
mA
µA
mA
V
V
V
V
V
Ω
mA
µA
kΩ
V
V
mA
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Continued on the next page...
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
A3930
and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued):
at T
J
= –40°C to 150°C, V
BB
= 7 to 45 V, unless otherwise noted
[1]
Characteristics
LOGIC INPUTS AND OUTPUTS
FFx Fault Output (Open Drain)
FFx Fault Output Leakage Current
[2]
TACHO and DIRO Output High Voltage
TACHO and DIRO Output Low Voltage
Input Low Voltage
Input High Voltage (Except RESET)
RESET Input High Voltage
Input Hysteresis
Input Current (Except H1, H2, H3, and RESET)
[2]
RESET Input Pull-Down Resistor
Hx Input Pull-Up Resistor
CURRENT SENSE DIFFERENTIAL AMPLIFIER
Input Bias Current
[2]
Input Offset Current
[2]
CSP Input Resistance
CSN Input Resistance
Differential Input Voltage
Output Offset Voltage
Output Offset Voltage Drift
Input Common Mode Range
Differential Input Voltage Gain
Low Output Voltage Error
DC Common Mode Gain
Source Resistance
Output Dynamic Range
Output Current – Sink
Output Current – Source
[2]
Supply Rejection
Small Signal 3 dB Bandwidth Frequency
Settling Time
AC Common Mode Gain
Common Mode Recovery Time
Output Slew Rate
Input Overload Recovery Time
I
IBS
I
IOS
R
CSP
R
CSN
V
ID
V
OOS
V
OOS(∆t)
V
CM
A
V
V
err
A
CMdc
r
CSOUT
V
CSOUT
I
CSOUT(sink)
I
CSOUT(source)
PSRR
f
3dB
t
SETTLE
A
CMac
t
CMrec
SR
t
IDREC
CSP = CSN = 0 V
CSP = CSN = 0 V
Measured with respect to AGND
Measured with respect to AGND
V
ID
= CSP – CSN, –1.3 V < CSP < 4 V, –1.3
V < CSN < 4 V
CSP = CSN = 0 V
CSP = CSN = 0 V
CSP = CSN
40 mV < V
ID
< 175 mV, V
CM
in range
0 < V
ID
< 40 mV,
V
CSOUT
= (19 × V
ID
) + V
OOS
+ V
err
CSP = CSN = 200 mV
V
CSOUT
= 2 V, –2 mA < I
CSOUT
< 0.5 mA
–100 µA < I
CSOUT
< 100 µA
V
CSOUT
= 2 V ±5%
V
CSOUT
= 2 V ±5%
CSP = CSN = AGND, 0 to 300 kHz
V
ID
=10 mV
PP
To within 10%, V
CSOUT
= 1 V
PP
square wave
V
ICR
= 250 mV
PP
, 0 to 1 MHz
To within 100 mV, V
ICR
= +4.1 to 0 V step
10% to 90% points, V
ID
= 0 to 175 mV step
To within 10%, V
ID
=250 mV to 0 V step
–250
–10
–
–
0
100
–
–1.5
18.5
–20
–
–
0.1
–
–
–
–
–
–
–
–
–
–200
–
80
4
–
320
100
–
19
–
–30
80
–
1
–19
45
1.6
400
–28
1
20
500
–150
10
–
–
200
550
–
4
19.5
20
–
–
V
5
–
0.2
–
–
–
–
–
–
–
–
–
µA
µA
kΩ
kΩ
mV
mV
µV/°C
V
V/V
mV
dB
Ω
V
mA
mA
dB
MHz
ns
dB
µs
V/µs
ns
V
OL
I
OH
V
OH
V
OL
V
IL
V
IH
V
IHR
V
IHys
I
IN
R
PD
R
PU
V
IN
= 5 V
V
IN
= 0 V
I
OL
= 1 mA, fault asserted
V
O
= 5 V, fault not asserted
I
OH
= –1 mA
I
OL
= 1 mA
–
–1
V
5
– 1 V
–
–
2
2.2
300
–1
–
–
–
–
–
–
–
–
–
500
–
50
100
0.4
1
–
0.4
0.8
–
–
–
1
–
–
V
µA
V
V
V
V
V
mV
µA
kΩ
kΩ
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Continued on the next page…
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
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