IR3510
DATA SHEET
HOT-SWAP N+1 REDUNDANT XPHASE CONTROL IC
DESCRIPTION
The IR3510 Hot-Swap N+1 Redundant X-Phase Controller combines input isolation control for hot-
swappable application, X-Phase VRM/VRD control and output OR-ing control for N+1 redundant
application. It interfaces with microcontroller and X-Phase phase ICs to provide a full featured and
flexible solution for powering high-end CPUs and servers.
The IR3510 interfaces with system logic to receive “ENABLE”, “VSET” which is the analog reference
voltage for controlling VRM output voltage, constant current limit “OCPSET” and OVP limit “OVPSET”.
It feeds back to the system load current “IO”, VRM status “VRRDY”, OR-ing FETs status “ORING” and
input fault “IOCD”.
The IR3510 works with existing X-Phase phase ICs to provide a full featured multiphase VRM control,
including soft-start, voltage regulation, constant current limit, remote sense and open sense leads
protection.
The IR3510 continuously monitors the 12V input current and VRM output voltage. Once the input
current exceeds the programmable threshold, it goes to current limit mode and turn off the input FETs
when the OC delay times out. It immediately turns off the input FETs when an OV condition is detected
on the VRM output. It also has UVLO for both the 12V input and the supply voltage to the VRM.
The IR3510 has built-in OR-ing control function for N+1 redundant application. When the VRM output
voltage is higher than the output voltage bus, it turns on the OR-ing FETs; When the VRM output is
sinking current from the output voltage bus, it turns off the OR-ing FETs.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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Two ENABLE thresholds for turning on input FET and VRM output
Input isolation FET control for hot-swap, input OCP and output OVP
Programmable input OCP limit and delay
Input isolation FET short detection
Integrated Charge Pump drives input isolation FETs and output OR-ing FETs
Programmable 150KHz to 1MHz oscillator
Programmable two-stage soft-start
Analog voltage setting for output voltage control, OVP limit and OCP limit
True remote voltage sense with open-sense-lead protection
Programmable output impedance
Gain adjustable analog load current report with thermal compensation capability
Average Current Mode control improving current sharing between paralleled modules
Constant output current limit
Compatible with existing IR3086A and IR3088A Phase ICs
OR-ing control with adjustable reverse current cut-off threshold
Input Fault, VRRDY and OR-ing status indications
Operation from 12V input with 9V Under-Voltage Lockout
6.8V Bias Voltage provides system reference
32-lead MLPQ 5x5mm package
Page 1 of 36
IR Confidential
May 18, 2009
IR3510
APPLICATION CIRCUIT
IRF6635
+12V IN
IRF6631
IRF6635
Rs 1m/1W
L
C11
C12
C13
IRF6635
GND
C3
1n
Rocset
2k
GND
C14
VO+
C4
10n
C2 1u
R1 10
31
30
29
VBIAS
C1
0.1u
1
Cx 0.1u
2
3
4
5
6
7
8
27
26
25
32
28
Radj
1k
VBIAS
Rosc 41.2k
24
23
22
21
20
C8 100p
19
R11 1K
18
R10 2k
17
R8
1k
R9 2k
NTC
C7 10n
R12 10K
GAT E_O
OR +
OR -
IC S+
IC S-
GAT E_I
LGN D
ROSC
C19
10n
VDAC
RMPOUT
ISHARE
EAOUT
VCC
ENABLE
VRRDY
ORING
VSET
OVP_LIMIT
OCP_LIMIT
CX
ENABLE
VRRDY
ORING
VSET
OVPSET
OCPSET
SS
U1
IR3510
VREF
RMPOUT
IIN
EAOUT
IFB
IO
VOSN S-
VOSN S+
OVPSN S
Rt
CURRENT
IOC D
IGAIN
VO
VF B
14
15
IR EF
16
10
IOCD
Css
0.1u
Cd
C6 100p
10n
R4
1k
R7
10k
C5
10n
R6
100k
32
31
30
29
28
VBIAS
27
26
25
PACKAGE
11
12
13
9
GATE_O
OR+
OR-
ICS+
ICS-
GATE_I
LGND
ROSC
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
VCC
CX
ENABLE
VRRDY
ORING
VSET
OVPSET
OCPSET
SS
U1
IR3510
VREF
RMPOUT
IIN
EAOUT
IFB
IO
VOSNS-
VOSNS+
OVPSNS
IOCD
IGAIN
VO
VFB
14
15
IREF
16
9
10
( MLPQ-32, 5x5 mm, 34°C/W )
Page 2 of 36
IR Confidential
11
12
13
May 18, 2009
IR3510
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature…………….. 0 C to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………3
o
Reflow Temperature…………………………….260 C
o
o
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN NAME
VCC
CX
ENABLE
VRRDY
ORING
VSET
OVPSET
OCPSET
SS
IOCD
VOSNS-
VOSNS+
OVPSNS
VO
VFB
IREF
IGAIN
IO
IFB
EAOUT
IIN
RMPOUT
VREF
ROSC
OR-
OR+
GATE_O
LGND
GATE_I
ICS-
ICS+
VBIAS
V
MAX
20V
30V
20V
20V
20V
10V
10V
10V
10V
10V
0.5V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
10V
25V
n/a
30V
20V
20V
10V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V DC, -2V for
100ns
n/a
-0.3V DC, -2V for
100ns
-0.3V
-0.3V
-0.3V
I
SOURCE
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
10mA
1mA
5mA
1mA
20mA
1mA
5mA
1mA
1mA
10mA
1mA
1mA
1mA
1A for 100ns,
200ma DC
50mA
1A for 100ns,
200ma DC
1mA
1mA
200mA
I
SINK
200mA
1mA
1mA
20mA
20mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
10mA
1mA
5mA
1mA
10mA
1mA
5mA
1mA
1mA
1mA
1mA
1mA
1mA
1A for 100ns,
200ma DC
1mA
1A for 100ns,
200ma DC
1mA
1mA
50mA
Page 3 of 36
IR Confidential
May 18, 2009
IR3510
PIN DESCRIPTION
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN NAME
VCC
CX
ENABLE
VRRDY
ORING
VSET
OVPSET
OCPSET
SS
IOCD
VOSNS-
VOSNS+
OVPSNS
VO
VFB
IREF
IGAIN
IO
IFB
EAOUT
IIN
RMPOUT
VREF
ROSC
OR-
OR+
GATE_O
LGND
GATE_I
ICS-
ICS+
VBIAS
PIN DESCRIPTION
Power input for internal circuitry.
Connect external cap for charge pump
Enable input. Lower level threshold turns on input FET, Higher level threshold
turns on VRM output.
Open collector output indicating VRM soft-start end and no fault.
Open collector output indicating the OR-ing FET is on
Analog input sets VRM no-load output voltage. Non-inverting input to voltage
error amplifier.
Analog input sets the OVP threshold which is relative to VSET.
Analog input sets the constant current limit threshold.
Connect a capacitor to LGND to set input and output soft-start time.
Connect a cap to LGND to set input OCP delay. Logic HIGH indicating input
Fault.
Remote sense amplifier input. Connect to ground at the load.
Remote sense amplifier input. Connect to output at load.
OVP sense input. Connect resistor divider to VO to program OVP threshold.
Remote sense amplifier output.
Inverting input to the voltage error amplifier.
Voltage error amplifier output.
Inverting input to current report amplifier. Connecting external resistor divider
to set gain.
Analog output represents the VRM average output current.
Current feedback to the inverting input of current error amplifier.
Output of the current error amplifier.
Average phase current sense input from the phase ICs.
Oscillator Output voltage. Used by Phase ICs to program phase timing
Buffered VSET, output to phase ICs VDAC pin.
Connect a resistor to LGND to set oscillator frequency.
Output voltage at the DRAIN side of OR-ing FET.
Output voltage at the SOURCE side of OR-ing FET.
OR-ing FET gate drive signal.
Local Ground for internal circuitry and IC substrate connection
Input isolation FET gate signal
Inverting input to the input current sense amplifier.
Non-inverting input to the input current sense amplifier.
6.75V regulated output used as a system reference voltage for internal
circuitry and the Phase ICs. It can also be used as external reference.
Page 4 of 36
IR Confidential
May 18, 2009
IR3510
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 8.1V
≤
VCC
≤
16V, 0 C
≤
T
J
≤
100 C, Rosc = 42K
PARAMETER
VBIAS Regulator
Output Voltage
Charge Pump
Output Voltage Above VCC
Output Voltage Above VCC
Voltage Clamp
Input UVLO1
Start Threshold Voltage
Stop Threshold Voltage
Hysteresis
ENABLE Input
Enable 1Threshold Voltage
Enable 1Threshold Voltage
Hysteresis
Enable 2Threshold Voltage
Enable 2Threshold Voltage
Hysteresis
Pull-up Voltage
Pull-up Resistance
Input Resistance
Input Fault Latch Reset Falling
Edge Delay
Soft-Start
SS to VFB Input Offset Voltage
Soft-Start Time
Charge Voltage
Charge Comparator Threshold
Voltage
Charge Comparator Threshold
Voltage
Charge Comparator Hysteresis
Discharge Time
Discharge Comparator Threshold
VRRDY Output Voltage
VRRDY Output Voltage
VRRDY Leakage Current
Page 5 of 36
I(VRRDY) = 4mA
V(VCC) = 2V, I(VRRDY) = 1mA
V(VRRDY) = 3.3V
1V
≤
V(SS)
≤
3.5V
Relative to Charge Voltage,
V(SS) rising
Relative to Charge Voltage,
V(SS) falling
Note 2
V(ENABLE) > 0.95V
V(ENABLE) rising
V(ENABLE) falling
V(ENABLE) rising
V(ENABLE) falling
0.5
0.45
25
1.05
1.0
25
0.825
5
50
1.2
0.6
0.55
50
1.15
1.1
50
0.875
10
100
2
0.7
0.65
75
1.25
1.2
75
0.925
20
200
2.8
V
V
mV
V
V
mV
V
Κ
Κ
us
Note 1
Note 1
8.7
7.95
0.6
9
8.2
0.8
9.3
8.5
1.0
V
V
V
9V
≤
V(VCC)
≤
16V, Cx = 0.01uF
V(VCC) = 9V, Cx = 0.01uF
6
5.3
25
27
29
V
V
V
-20mA
≤
I(VBIAS)
≤
0mA
C(VBIAS) = 1u
6.5
6.75
7.0
V
TEST CONDITION
MIN
TYP
MAX
UNIT
o
o
With V(VFB) = 0V, adjust V(SS)
until V(IREF) drives high
Css = 0.1u
0.75
3.5
3.575
40
105
40
50
180
0
0
1.35
5
3.775
80
145
65
225
230
150
150
0
1.6
10
3.975
140
200
90
500
280
400
400
10
V
ms
V
mV
mV
mV
us
mV
mV
mV
µA
IR Confidential
May 18, 2009