A3972
Dual DMOS Full-Bridge Microstepping PWM Motor Driver
Features and Benefits
▪
±1.5 A, 50 V Continuous Output Rating
▪
Low R
DS(on)
DMOS Output Drivers
▪
Optimized Microstepping via 6-Bit Linear DACs
▪
Programmable Mixed, Fast, and Slow Current-Decay
Modes
▪
4 MHz Internal Oscillator for Digital Timing
▪
Serial-Interface Controls Chip Functions
▪
Synchronous Rectification for Low Power Dissipation
▪
Internal UVLO and Thermal Shutdown Circuitry
▪
Crossover-Current Protection
▪
Precision 2 V Reference
▪
Inputs Compatible with 3.3 or 5 V Control Signals
▪
Sleep and Idle Modes
Description
Designed for pulse-width modulated (PWM) current control
of bipolar microstepping stepper motors, the A3972 is capable
of continuous output currents to ±1.5 A and operating voltages
to 50 V. Internal fixed off-time PWM current-control timing
circuitry can be programmed via a serial interface to operate
in slow, fast, and mixed current-decay modes.
The desired load-current level is set via the serial port with
two 6-bit linear DACs in conjunction with a reference voltage.
The six bits of control allow maximum flexibility in torque
control for a variety of step methods, from microstepping to
full-step drive. Load current is set in 1.56% increments of the
maximum value.
Synchronous rectification circuitry allows the load current
to flow through the low R
DS(on)
of the DMOS output driver
during the current decay. This feature will eliminate the
need for external clamp diodes in most applications, saving
cost and external component count, while minimizing power
dissipation.
Internal circuit protection includes thermal shutdown with
hysteresis, transient-suppression diodes, and crossover-current
protection. Special power-up sequencing is not required.
The A3972SB is supplied in a 24-pin plastic DIP with two
batwing power tabs (suffix ‘B’). The power tabs are at ground
potential and need no electrical isolation. The device is lead
(Pb) free with 100% matte tin leadframe plating.
Package: 24-pin DIP with 4 fused leads
(suffix B)
Not to scale
Pin-out Diagram
29319.33, Rev. D
A3972
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
Selection Guide
Part Number
A3972SB-T
15 pieces/tube
Packing
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Output Current*
Logic Supply Voltage
Logic Input Voltage Range
Reference Voltage
Sense Voltage (DC)
Package Power Dissipation
Operating Ambient Temperature
Junction Temperature
Storage Temperature
Symbol
V
BB
I
OUT
V
DD
V
IN
V
REF
V
S
P
D
T
A
T
J
T
stg
Range S
Notes
Rating
50
±1.5
7.0
–0.3 to V
DD
+ 0.3
3
500
3.1
–20 to 85
150
–55 to 150
Units
V
A
V
V
V
mV
W
ºC
ºC
ºC
*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed
the specified current rating or a junction temperature of 150°C.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3972
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
FUNCTIONAL BLOCK DIAGRAM
0.22 F
0.22 F
22
V
REG
CP2
3
2
CP1
LOGIC
SUPPLY
2V
15
V
DD
UVLO AND
FAULT
DETECT
REGULATOR
BANDGAP
V
CP
LOAD
SUPPLY
CHARGE PUMP
1
V
BB1
5
0.22 F
MUX
14
6-BIT
LINEAR
DAC
+
6
DMOS H-BRIDGE
SENSE
1
V
CP
-
OUT
1A
9
OSCILATOR
OSC
24
PROGRAMMABLE
PWM TIMER
FIXED-OFF
BLANK
MIXED DECAY
OUT
1B
4
OSC SELECT/
DIVIDER
8
SENSE
1
CLOCK
11
DATA
12
STROBE
10
SERIAL
PORT
CONTROL
LOGIC
PHASE 1/2
SYNC. RECT. MODE
SYNC. RECT. DISABLE
MODE 1/2
GATE
DRIVE
DMOS H-BRIDGE
0.1 F
20
V
BB2
SLEEP
23
OUT
2A
16
PROGRAMMABLE
PWM TIMER
2V
6
FIXED-OFF
BLANK
MIXED DECAY
OUT
2B
21
REF
13
BUFFER
+
6-BIT
LINEAR
DAC
-
SENSE
2
17
0.1 F
6
GROUND
7
18 19
Dwg. FP-050-1
Copyright © 2000, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3972
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
BB
= 50 V, V
DD
= 5.0 V, V
S
= 0.5 V,
f
PWM
< 50 kHz (unless otherwise noted).
Limits
Characteristic
Load Supply Voltage Range
Logic Supply Voltage Range
Load Supply Current
Symbol
V
BB
V
DD
I
BB
Test Conditions
Operating
During sleep mode
Operating
f
PWM
< 50 kHz
Operating, outputs disabled
Sleep or idle mode
Logic Supply Current
I
DD
f
PWM
< 50 kHz
Outputs off
Idle mode (D0 = 1, D18 = 0)
Sleep mode
Output Drivers
Output Leakage Current
Output On Resistance
Body Diode Forward Voltage
I
DSS
r
DS(on)
V
F
V
OUT
= V
BB
V
OUT
= 0 V
Source driver, I
OUT
= –1.5 A
Sink driver, I
OUT
= 1.5 A
Source diode, I
F
= 1.5 A
Sink diode, I
F
= 1.5 A
Control Logic
Logic Input Voltage
Logic Input Current
OSC Input Frequency Range
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
f
OSC
V
IN
= 2.0 V
V
IN
= 0.8 V
Divide by one
(D0 =1, D13 = 0, D14 = 1)
OSC Input Duty Cycle
Input Hysterisis
—
V
IN
40
0.20
—
—
60
0.40
%
V
2.0
—
—
—
2.5
—
—
<1.0
<-2.0
—
—
0.8
20
-20
6.0
V
V
μA
μA
MHz
—
—
—
—
—
—
<1.0
<-1.0
0.5
0.315
—
—
50
-50
0.55
0.35
1.2
1.2
μA
μA
V
V
Min.
15
0
4.5
—
—
—
—
—
—
—
Typ.
—
—
5.0
—
—
—
—
—
—
—
Max.
50
50
5.5
8.0
6.0
20
12
10
1.5
100
Units
V
V
V
mA
mA
μA
mA
mA
mA
μA
continued next page ...
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3972
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
BB
= 50 V, V
DD
= 5.0 V, V
S
= 0.5 V,
f
PWM
< 50 kHz (unless otherwise noted).
Limits
Characteristics
Control Logic (continued)
Internal Oscillator
DAC Accuracy (total error)
Reference Input Voltage Range
Reference Buffer Offset
Reference Divider Ratio
Reference Input Current
Internal Reference Voltage
Gain (G
m
) Error (note 3)
f
OSC
E
T
V
REF(EXT)
V
OS
V
REF
/V
S
I
REF
V
REF(INT)
E
G
D0 = 0, D17 = 0,
D18 = 0, DAC = 63
D18 = 0, DAC = 31
D18 = 1, DAC = 63
D18 = 1, DAC = 15
Comparator Input Offset Voltage
Propagation Delay Times
V
IO
t
pd
V
REF
= 0 V
50% to 90%:
PWM change to source on
PWM change to source off
PWM change to sink on
PWM change to sink off
Crossover Dead Time
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
t
dt
T
J
T
J
V
UVLO
V
UVLO
Increasing V
DD
D0 = 0, D18 = 0
D0 = 0, D18 = 1
V
REF
= 2.0 V
OSC shorted to ground
R
OSC
= 51 k
Relative to DAC reference buffer
output, D0 = 0, D17 = 0
0.5
—
—
—
—
1.94
—
—
—
—
—
500
50
500
50
300
—
—
3.9
0.05
—
±10
8.0
4.0
—
2.0
0
0
0
0
±5.0
800
150
800
150
700
165
15
4.2
0.10
2.6
—
—
—
±0.5
2.06
±6
±9
±6
±10
—
1200
350
1200
350
900
—
—
4.45
—
V
mV
—
—
μA
V
%
%
%
%
mV
ns
ns
ns
ns
ns
°C
°C
V
V
3.0
3.4
—
4.0
4.0
±1/2
5.0
4.6
—
MHz
MHz
LSB
Symbol
Test Conditions
Min.
Typ.
Max.
Units
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. E
G
= [(V
REF
/Range) – V
S
]/(V
REF
/Range).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
