HI-8425, HI-8426
October 2013
8-Channel, Ground /Open, or Supply / Open Sensor
4-channel 200 mA Ground / Open Driver
·
Airbus ABD0100H compliant
·
4 Low-Side 200 mA drivers
·
4.5 Ohm On Resistance
·
Over-Current Fault Detection Signaled by Logic Output
·
Max Power Dissipation Automatically Limited by
Fault Protection
·
Diode Clamps for Discharging Inductive Loads
GENERAL DESCRIPTION
The HI-8425 is a combined 8-channel discrete-to-digital
sensor and quad low side driver fabricated with Silicon-on-
Insulator (SOI) technology for robust latch-up free
operation. Sense detection can either be GND/Open or
Supply/Open as configured by the SNSE_SEL pin.
Supply/Open sensing is also referred to as 28V/Open
sensing. The sensing circuit window comparator thresholds
can be fixed at the internal programmed values or can be
set externally at the HI_SET and LO_SET pins, as selected
by the THS_SEL pin. The digital SENSE outputs can be tri-
stated by taking the OE pin high.
All sense inputs are internally lightning protected to
DO160G, Section 22, Cat AZ, BZ and ZZ without external
components.
The HI-8425 also offers four low side switches each
capable of sinking 200 mA of current. Each switch transistor
is controlled by its own digital input pin and is fully fault
protected. Over-current conditions, such as a short circuit,
are detected and inhibited while signaling the fault
condition at the corresponding logic output. These four
FAULT outputs are also available in a combined OR output.
The outputs are fully protected from transients when driving
relays.
The HI-8426 puts all of the features of the HI-8425 except
the individual Fault Detection Outputs, Tri-state pin
selection and fixed internal thresholds into a 32-pin Chip
Scale Package (QFN) which measures only 5mm x 5mm.
Interface to the digital subsystem is simple CMOS logic
inputs and outputs. The logic pins are compatible with 5V or
3.3V logic allowing direct connection to a wide range of
microcontrollers or FPGAs.
APPLICATIONS
·
Relay Driver
·
Lamp driver
·
Discrete Signaling
·
Avionics Discrete to Digital Sensing
PIN CONFIGURATIONS
40 - VLOGIC
39 - THS_SEL
38 - HI_SET
37 - LO_SET
36 - SNSE_SEL
35 - FAULT_OR
34 - DSEL_0
33 - DSEL_1
32 - DSEL_2
31 - DSEL_3
VWET - 1
SENSE0 - 2
SENSE1 - 3
SENSE2 - 4
SENSE3 - 5
SENSE4 - 6
SENSE5 - 7
SENSE6 - 8
SENSE7 - 9
OE - 10
HI-8425PCI
HI-8425PCT
HI-8425PCM
30 -
29 - FAULT_0
28 - DRV_0
27 - DRV_1
26 - FAULT_1
25 - GND
24 - FAULT_2
23 - DRV_2
22 - DRV_3
21 - FAULT_3
40 Pin Plastic 6mm x 6mm
Chip-scale package (QFN)
32 - VWET
31 - VLOGIC
30 - HI_SET
29 - LO_SET
28 - SNSE_SEL
27 - DSEL_0
26 - DSEL_1
25 - DSEL_2
SO_0 - 11
SO_1 - 12
SO_2 - 13
SO_3 - 14
SO_4 - 15
SO_5 - 16
SO_6 - 17
SO_7 - 18
GND - 19
- 20
SENSE0 - 1
SENSE1 - 2
SENSE2 - 3
SENSE3 - 4
SENSE4 - 5
SENSE5 - 6
SENSE6 - 7
SENSE7 - 8
FEATURES
·
Robust CMOS Silicon-on-Insulator (SOI) technology
·
8-channel Selectable Sense Operation, GND/Open
or Supply/Open
·
Selectable Thresholds and Hysteresis
·
Sense Detection Range 3V to 22V
·
Logic Operation from 3.0V to 5.5V
·
Lightning Protected Sense Inputs
(DS8425 Rev. D)
HI-8426PCI
HI-8426PCT
HI-8426PCM
9
10
11
12
13
14
15
16
24 - DSEL_3
23 - DRV0
22 - DRV1
21 - GND
20 - DRV_2
19 - DRV_3
18 - FAULT_OR
17 - GND
32 Pin Plastic 5mm x 5mm
Chip-scale package (QFN)
(See page 15 for leaded QFP package options)
HOLT INTEGRATED CIRCUITS
www.holtic.com
10/13
SO_0
SO_1
SO_2
SO_3
SO_4
SO_5
SO_6
SO_7
-
-
-
-
-
-
-
-
HI-8425, HI-8426
BLOCK DIAGRAM
VLOGIC
VWET
V
LOGIC
THS_SEL
VREF_HI
VOLTAGE
REFERENCE
VREF_LO
VTHI/10
SNSE_SEL
HI_SET
LO_SET
VTLO/10
V
WET
V
LOGIC
SNSE_SEL
23.8K
+
-
29K
SENSE_0
SENSE_1
SENSE_2
SENSE_3
SENSE_4
SENSE_5
SENSE_6
SENSE_7
3.3K
LIGHTNING
PROTECTION
360K
40K
+
-
SNSE_SEL
SO_0
SO_1
SO_2
SO_3
SO_4
SO_5
SO_6
SO_7
OE
DSEL_0
DSEL_1
DSEL_2
DSEL_3
Drive
Control
DRV_0
DRV_1
DRV_2
DRV_3
Current
Sense
GND
FAULT_0
FAULT_1
FAULT_2
FAULT_3
FAULT_OR
GND
Figure 2
HOLT INTEGRATED CIRCUITS
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HI-8425, HI-8426
PIN DESCRIPTIONS
SYMBOL
VWET
SENSE0
SENSE1
SENSE2
SENSE3
SENSE4
SENSE5
SENSE6
SENSE7
OE
SO_0
SO_1
SO_2
SO_3
SO_4
SO_5
SO_6
SO_7
FAULT_3
DRV_3
GND
DRV_2
FAULT_2
FAULT_1
DRV_1
DRV_0
FAULT_0
DSEL_3
DSEL_2
DSEL_1
DSEL_0
SNSE_SEL
LO_SET
HI_SET
THS_SEL
VLOGIC
FUNCTION
Supply
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Digital Input
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Switch Output
Supply
Switch Output
Digital output
Digital output
Switch Output
Switch Output
Digital output
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Analog input
Analog input
Digital Input
Supply
DESCRIPTION
Optional input to supply relay wetting current to sense lines in GND/Open operation
50KΩ to GND
Discrete input 0. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
Discrete input 1. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
Discrete input 2. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
Discrete input 3. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
Discrete input 4. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
Discrete input 5. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
Discrete input 6. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
Discrete input 7. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
If High, SO_n and fault outputs are high-impedance. OE has internal 30KΩ pull-down resistor
High if SNSE_SEL=0 and SENSE0 < V
LO
, or Low if SNSE_SEL=1 and SENSE0 > V
HI
High if SNSE_SEL=0 and SENSE1 < V
LO
, or Low if SNSE_SEL=1 and SENSE1 > V
HI
High if SNSE_SEL=0 and SENSE2 < V
LO
, or Low if SNSE_SEL=1 and SENSE2 > V
HI
High if SNSE_SEL=0 and SENSE3 < V
LO
, or Low if SNSE_SEL=1 and SENSE3 > V
HI
High if SNSE_SEL=0 and SENSE4 < V
LO
, or Low if SNSE_SEL=1 and SENSE4 > V
HI
High if SNSE_SEL=0 and SENSE5 < V
LO
, or Low if SNSE_SEL=1 and SENSE5 > V
HI
High if SNSE_SEL=0 and SENSE6 < V
LO
, or Low if SNSE_SEL=1 and SENSE6 > V
HI
High if SNSE_SEL=0 and SENSE7 < V
LO
, or Low if SNSE_SEL=1 and SENSE7 > V
HI
High if Driver 3 is attempting to sink excess current
Drain node of Ground switch driver 3
Ground for logic and Analog Ground return for DRV0-3. GND pin and the isolated backside pad should
be grounded for optimum performance and power dissipation.
Drain node of Ground switch driver 2
High if Driver 2 is attempting to sink excess current
High if Driver 1 is attempting to sink excess current
Drain node of Ground switch driver 1
Drain node of Ground switch driver 0
High if Driver 0 is attempting to sink excess current
When high, turns on Driver 3. DSEL_3 has an internal 30KΩ pull-down resistor
When high, turns on Driver 2. DSEL_2 has an internal 30KΩ pull-down resistor
When high, turns on Driver 1. DSEL_1 has an internal 30KΩ pull-down resistor
When high, turns on Driver 0. DSEL_0 has an internal 30KΩ pull-down resistor
High if any Driver is attempting to sink excess current
If Low, SENSE pins are sensing Open/Gnd. If High, SENSE pins sense SUPPLY/Open
If THS_SEL is High, this pin sets the lower window comparator threshold
If THS_SEL is High, this pin sets the upper window comparator threshold
If THS_SEL is Low, comparator thresholds are set internally. THS_SEL has an internal 30KΩ pull-up
Logic supply. (3.0V - 5.5V)
FAULT_OR Digital Output
HOLT INTEGRATED CIRCUITS
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HI-8425, HI-8426
FUNCTIONAL DESCRIPTION
SENSING
The 8 Sense Channels can be configured to meet the
requirements of a variety of conditions and applications.
Table 1 summarizes basic function selection and Table 2
gives more details on possible threshold values.
WETTING CURRENT
For GND/Open applications with VWET open, the wetting
current with the input voltage at GND is simply (VLOGIC -
0.75)/3.3K. When applying a higher voltage at the VWET
pin the wetting current is (VLOGIC - 0.75)/3.3K + (VWET -
4.2)/127K. Additional wetting current can be achieved by
placing an external resistor and a diode between VWET
and the individual sense inputs.
GND/OPEN SENSING
For GND/Open sensing, the SNS_SEL pin is connected to
GND. Referring to the Block Diagram, Figure 2, this selection
will connect a 3.3KΩ pull-up resistor through a diode to
VLOGIC and a 23.8KΩ resistor through 3 diodes to VWET.
These resistors give extra noise immunity for detecting the
open state while providing relay wetting current. Configuring
THS_SEL, HI_SET/LO_SEL and VWET as described below
sets the window comparator thresholds, V
THI
and V
TLO
, the
open input voltage when open, and the input current.
SUPPLY/OPEN SENSING
The 8 Sense Channels can be configured to sense
Supply/Open by connecting the SNSE_SEL pin to
VLOGIC. Refering to Figure 2, a 32KΩ resistor is switched
in series to provide a pull down in addition to the 400KΩ of
the comparator input divider to GND. Similar to the
GND/Open case configuring THS_SEL, HI_SET/LO_SEL
and VWET as described below sets the window compara-
tor thresholds, the open input voltage when open and the
wetting current.
THRESHOLD SELECT
The threshold selections are handled in the same way as
stated above for the GND/OPEN case.
For THS_SEL set low, the internal reference nominally
sets the window comparator. See table 2 for the
V
THI
and
V
THLO
threshold levels.
For THS_SEL set high, the final thresholds are 10X the
voltage set on the HI_SET and LO_SET pins. The VWET
pin must be left open in the Supply/Open sensing case.
WETTING CURRENT
For the Supply/Open case the wetting current into the
sense input is the current sunk by the effective 28KΩ to
GND. For V
SENSE_n
= 28V, I
WET
is 1ma. See Figure 12.
HI-8425 (40 pin version) - THRESHOLD SELECT
The HI-8425 offers a choice between internally fixed
thresholds or external thresholds provided by the user.
With THS_SEL set to GND, the window comparator
thresholds are fixed based on an internal reference. The high
threshold, V
THI
, and the low threshold, V
THLO
levels may be
found in Table 2. When the internal references are used the
HI_SET and LO_SET pins should be connected to GND.
For applications with either large GND offsets or thresholds
higher than VLOGIC - 0.75V, THS_SEL is set high and the
thresholds are set externally, for example by a simple
resistor divider off the VLOGIC supply. In this case V
THI
is
equal to 10X the voltage on the HI_SET pin.
V
TLO
is equal to
10X the voltage on the LO_SET pin. This mode allows the
user complete flexibility to define the thresholds and
hysteresis levels.
HI-8426 (32 pin version) THRESHOLD SELECT
For applications that can take advantage of the very small 32
pin chip scale package of the HI-8426, THS_SEL is not
available and an internal pull-up makes it mandatory to
supply HI_SET and LO_SET externally.
Table 1. Function Table
SENSE_n
Open or > VTHI
< VTLO
X
Open or < VTLO
> VTHI
X
L
L
L
H
H
H
SNSE_SEL
(GND/OPEN)
(GND/OPEN)
(GND/OPEN)
(V+/OPEN)
(V+/OPEN)
(V+/OPEN)
OE
L
L
H
L
L
H
SO_n
L
H
Z
H
L
Z
OPEN INPUT VOLTAGE
For correct operation, the V
SENSE_n
when open, must be
higher than
V
THI
so SO_n will be low. This condition requires
VWET to be set greater than (VTHI/0.9 + 2.25V)
. Various
ARINC standards such as ARINC 763 define t
he standard
“Open” signal as characterized by a resistance of 100KΩ or
more with respect to signal common. The user should
consider this 100KΩ to ground case when setting the
thresholds.
H = VLOGIC, L = GND, Z = Hi-Z, X = Don’t Care, V+ = V
SUPPLY
See Table 2 for values of VTHI/VTLO
HOLT INTEGRATED CIRCUITS
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HI-8425, HI-8426
FUNCTIONAL DESCRIPTION
Table 2. Configuration options and allowed threshold values -55C to 125C.
VWET
Pin
SNSE_ THS_
SEL
SEL
Threshold
Selected
Maximum
HI_SET
(VTHI =
HI_SETx10)
-
-
-
0.4V (4.0V)
0.4V (4.0V)
2.2V (22V)
-
2.2V (22V)
-
-
-
0.4V (4.0V)
0.4V (4.0V)
2.2V (22V)
-
2.2V (22V)
Minimum
LO_SET
(VTLO =
LO_SETx10)
-
-
-
0.3V (3.0V)
0.3V (3.0V)
0.3V (3.0V)
-
0.3V (3.0V)
-
-
-
0.3V (3.0V)
0.3V (3.0V)
0.3V (3.0V)
-
0.3V (3.0V)
Guaranteed
High
Threshold
2.5V
2.7V
2.55V
VTHI + 0.5V
VTHI + 0.5V
VTHI + 0.5V
15.5V
VTHI + 0.5V
3.25V
3.75V
3.5V
VTHI + 0.5V
VTHI + 0.5V
VTHI + 0.5V
15.5V
VTHI + 0.5V
Guaranteed
Low
Threshold
1.0V
1.0V
1.0V
VTLO - 0.5V
VTLO - 0.5V
VTLO - 0.5V
11.0V
VTLO - 0.5V
1.0V
1.0V
1.0V
VTLO - 0.5V
VTLO - 0.5V
VTLO - 0.5V
11.0V
VTLO - 0.5V
VLOGIC
Operation
3.0V
3.6V
3.3V
3.0V
3.6V
3.0V to 3.6V
3.0V to 3.6V
3.0V to 3.6V
4.5V
5.5V
5.0V
4.5V
5.5V
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
OPEN
OPEN
28V
7V
7V
28V
OPEN
OPEN
OPEN
OPEN
28V
7V
7V
28V
OPEN
OPEN
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
L
L
H
H
H
L
H
L
L
L
H
H
H
L
H
GND/OPEN
GND/OPEN
GND/OPEN
GND/OPEN
GND/OPEN
GND/OPEN
V+/OPEN
V+/OPEN
GND/OPEN
GND/OPEN
GND/OPEN
GND/OPEN
GND/OPEN
GND/OPEN
V+/OPEN
V+/OPEN
Internal
Internal
Internal
External
External
External
Internal
Exernal
Internal
Internal
Internal
External
External
External
Internal
External
NOTE:
VTHI = Sense pin high threshold (HI_SET x 10), VTLO = Sense pin low threshold (LO_SET x 10)
OUTPUT ENABLE
The output enable pin, OE, available on the HI-8425, tri-
states all Sense Outputs and Low Side Driver Fault Outputs
to allow connecting the tri-state outputs in parallel with other
tri-stated chips. The OE pin has a pull-down and when left
open will cause these digital outputs to be driven to their logic
levels. If the OE pin is High, these digital outputs are high
impedance.
OVER-CURRENT SHUTDOWN
Maximum DC power dissipation per driver is
approximately 0.5W at room temperature. Conditions that
would cause the power to exceed this amount will result in
a shut down of the driver. Over-current shutdown is
initiated when the driver pin voltage is more than
approximately 1.5V from GND. However there is a delay of
approximately 11μsec before the shutdown actually occurs
giving the driver an opportunity to charge capacitive loads
and thereby avoid shutdown. Similarly, if the driver is on
and a high load is suddenly switched on, the over-current
shutdown will be delayed in activation. Note that even
when the over-current fault condition is present, the driver
pin is still sourcing a few milliamps. This low current
condition continues until the input is taken low or the load is
removed.
FAULT CONDITIONS
Each driver has a converter that translates an over-current
detection into a logic high output at its FAULT output. The
FAULT_OR output goes high if one or more FAULT outputs
are high. These outputs can be tri-stated by setting OE
high.
OUTPUT DRIVERS
LOW SIDE DRIVERS
Both product versions offer four Low Side Drivers. Each
driver (NMOS switch) is capable of sinking a minimum of
200mA while exhibiting a R
on
of 4.5Ω typical. Each output has
diode clamps for protection during inductive kick-back for
relay applications. Off-state leakage is typically less than
10nA at room temperature. The inputs, DSEL0 through
DSEL3, have internal pull-downs which hold off the drivers
until logic highs are presented.
HOLT INTEGRATED CIRCUITS
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