Data Sheet No. PD60349 revL
IR21141SSPbF/IR22141SSPbF
HALF-BRIDGE GATE DRIVER IC
Features
•
•
•
•
•
•
•
•
•
Floating channel up to 600 V or 1200 V
Soft over-current shutdown
Synchronization signal to synchronize shutdown with the other phases
Integrated desaturation detection circuit
Two stage turn on output for di/dt control
Separate pull-up/pull-down output drive pins
Matched delay outputs
Undervoltage lockout with hysteresis band
Lead free
Product Summary
V
OFFSET
I
O
+/- (min)
V
OUT
Deadtime matching (max)
Deadtime (typ)
Desat blanking time (typ)
DSH, DSL input voltage
threshold (typ)
Soft shutdown time (typ)
600 V or
1200 V max.
1.0 A / 1.5 A
10.4 V – 20 V
75 ns
330
ns
3
µs
8.0 V
9.25 µs
Description
The IR21141/IR22141 gate driver family is suited to drive a single half bridge
in power switching applications. These drivers provide high gate driving
capability (2 A source, 3 A sink) and require low quiescent current, which
allows the use of bootstrap power supply techniques in medium power
systems. These drivers feature full short circuit protection by means of power
transistor desaturation detection and manage all half-bridge faults by
smoothly turning off the desaturated transistor through the dedicated soft
shutdown pin, therefore preventing over-voltages and reducing
electromagnetic emissions. In multi-phase systems, the IR21141/IR22141
drivers communicate using a dedicated local network (SY_FLT and
FAULT/SD signals) to properly manage phase-to-phase short circuits. The
system controller may force shutdown or read device fault state through the
3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the signal immunity
from DC-bus noise, the control and power ground use dedicated pins
enabling low-side emitter current sensing as well. Undervoltage conditions in
floating and low voltage circuits are managed independently.
Package
24-Lead SSOP
Typical connection
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14-Aug-09
© 2009 International Rectifier
1
IR21141/IR22141SSPbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to V
SS
, all currents are defined positive into any lead The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
V
S
V
B
V
HO
V
CC
COM
V
LO
V
IN
V
FLT
V
DSH
V
DSL
dVs/dt
P
D
Rth
JA
T
J
T
S
T
L
High side offset voltage
High side floating supply voltage
IR21141
IR22141
High side floating output voltage (HOP, HON and SSDH)
V
B
- 25
-0.3
-0.3
V
S
- 0.3
-0.3
V
CC
- 25
V
COM
-0.3
-0.3
-0.3
V
S
-3
V
COM
-3
—
—
—
—
-55
—
V
B
+ 0.3
625
1225
V
B
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
V
B
+ 0.3
V
CC
+ 0.3
50
1.5
65
150
150
300
°
C
V/ns
W
°
C/W
V
Low side and logic fixed supply voltage
Power ground
Low side output voltage (LOP, LON and SSDL)
Logic input voltage (HIN, LIN and FLT_CLR)
Fault input/output voltage (FAULT/SD and SY_FLT)
High side DS input voltage
Low side DS input voltage
Allowable offset voltage slew rate
Package power dissipation @ T
A
≤
25 °
C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to V
SS
. The V
S
offset rating is tested with all supplies biased at a 15 V differential.
Symbol
V
B
V
S
V
HO
V
LO
V
CC
COM
V
IN
V
FLT
V
DSH
V
DSL
t
PWHIN
T
A
†
Definition
High side floating supply voltage
†
††
Min.
IR21141
IR22141
V
S
+ 11.5
V
SS
V
SS
V
S
V
COM
11.5
-5
V
SS
V
SS
V
S
- 2.0
V
COM
- 2.0
1
-40
Max.
V
S
+ 20
600
1200
V
S
+ 20
V
CC
20
5
V
CC
V
CC
V
B
V
CC
Units
High side floating supply offset voltage
High side output voltage (HOP, HON and SSDH)
Low side output voltage (LOP, LON and SSDL)
Low side and logic fixed supply voltage (Note 1)
Power ground
Logic input voltage (HIN, LIN and FLT_CLR)
Fault input/output voltage (FAULT/SD and SY_FLT)
High side DS pin input voltage
Low side DS pin input voltage
High side pulse width for HIN input
Ambient temperature
V
µs
125
°
C
††
While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output
drivers if the UV thresholds are not reached. A minimum supply voltage of 8V is recommended for the driver
to operate safely under switching conditions at VS pin (please refer to the “start-up sequence” in application
section of this document)
Logic operational for V
S
from V
SS
-5 V to V
SS
+600 V or 1200 V. Logic state held for V
S
from V
SS
-5 V to V
SS
-
V
BS
. For a negative spike on V
B
(referenced to V
SS
) of less than 200ns the IC will withstand a sustained peak
of -40V under normal operation and an isolated event of up to -70V peak spike (please refer to the Design
Tip DT97-3 for more details).
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© 2009 International Rectifier
2
IR21141/IR22141SSPbF
Static Electrical Characteristics
V
CC
= 15 V, V
SS
= COM = 0 V, V
S
= 600 V or 1200 V and T
A
= 25 ° unless otherwise specified.
C
Pins: V
CC
, V
SS
, V
B
, V
S
(refer to Fig. 1)
Symbol
V
CCUV+
V
CCUV-
V
CCUVH
V
BSUV+
V
BSUV-
V
BSUVH
I
LK
I
QBS
I
QCC
Definition
V
CC
supply undervoltage positive going threshold
V
CC
supply undervoltage negative going threshold
V
CC
supply undervoltage lockout hysteresis
(V
B
-V
S
) supply undervoltage positive going threshold
(V
B
-V
S
) supply undervoltage negative going threshold
(V
B
-V
S
) supply undervoltage lockout hysteresis
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Min
9.3
8.7
—
9.3
8.7
—
—
—
—
Typ
10.2
9.3
0.9
10.2
9.3
0.9
—
400
0.7
Max Units
11.4
10.3
—
11.4
10.3
—
50
800
2.5
mA
µA
V
V
S
= 0 V, V
S
= 600 V
or 1200 V
V
B
= V
S
= 600 V or
1200 V
V
IN
= 0 V or 3.3 V
no load
Test Conditions
Pins: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT (refer to Fig. 2, 3)
Symbol
V
IH
V
IL
V
IHSS
I
IN+
I
IN-
R
ON,FLT
R
ON,SY
Logic "1" input voltage
Logic "0" input voltage
Logic input hysteresis
Logic “1” input bias current (HIN, LIN, FLTCLR)
Logic “0” input bias current (FAULT/SD, SY_FLT)
Logic “0” input bias current
Logic “1” input bias current (FAULT/SD, SY_FLT)
FAULT/SD open drain resistance
SY_FLT open drain resistance
Definition
Min
2.0
—
0.2
—
0
-1
-1
—
—
Typ
—
—
0.4
330
—
—
—
60
60
Max
—
0.8
—
—
1
0
0
—
—
PW≤ 7 µs
µA
V
IN
= 0 V
V
IN
= 3.3 V
V
Units
Test Conditions
V
CC
= V
CCUV-
to 20 V
Pins: DSL, DSH (refer to Fig. 4)
The active bias is present only the IR21141and IR22141. V
DESAT
, I
DS
and I
DSB
parameters are referenced to COM and V
S
respectively for DSL and DSH.
Symbol
Definition
Min Typ Max Units
Test Conditions
V
DESAT+
V
DESAT-
V
DSTH
I
DS+
I
DS
-
I
DSB
High desat input threshold voltage
Low desat input threshold voltage
Desat input voltage hysteresis
High DSH or DSL input bias current
Low DSH or DSL input bias current
DSH or DSL input bias current
(IR21141 and IR22141 only)
7.2 8.0 8.8
6.3 7.0 7.7
—
—
1.0
21
—
—
µA
mA
V
DESAT
= V
CC
or V
BS
V
DESAT
= 0 V
V
DESAT
= (V
CC
or V
BS
) – 2 V
V
See Figs. 4,16
— -160 —
—
-20
—
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© 2009 International Rectifier
3
IR21141/IR22141SSPbF
Pins: HOP, LOP (refer to Fig. 5)
Symbol
V
OH
Definition
High level output voltage, V
B
– V
HOP
or V
CC
–V
LOP
Min
—
Typ
40
Max Units Test Conditions
300
mV
I
O
= 20 mA
V
HOP/LOP
= 0 V, H
IN
or L
IN
= 1, PW≤
200 ns, resistive
load, see Fig. 8
A
Output high second stage short circuit pulsed current
V
HOP/LOP
= 0 V, H
IN
or L
IN
= 1,
400 ns
≤PW≤
10
µs, resistive load,
see Fig. 8
I
O1+
Output high first stage short circuit pulsed current
1
2
—
I
O2+
0.5
1
—
Pins: HON, LON, SSDH, SSDL (refer to Fig. 6)
Symbol
V
OL
R
ON,SSD
I
O-
Definition
Low level output voltage, V
HON
or V
LON
Soft Shutdown on resistance
†
Min
—
—
1.5
Typ
45
90
3
Max Units Test Conditions
300
—
—
A
mV
I
O
= 20 mA
PW≤ 7 µs
V
HOP/LOP
= 15 V,
H
IN
or L
IN
= 0, PW≤
10 µs
Output low short circuit pulsed current
†
SSD operation only
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© 2009 International Rectifier
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IR21141/IR22141SSPbF
AC Electrical Characteristics
V
CC
= V
BS
= 15 V, V
S
= V
SS
and T
A
= 25 ° unless otherwise specified.
C
Symbol
t
on
t
off
t
r
t
f
t
on1
t
DESAT1
t
DESAT2
t
DESAT3
t
DESAT4
t
DS
t
SS
t
SY_FLT,
DESAT1
Definition
Turn on propagation delay
Turn off propagation delay
Turn on rise time (C
LOAD
=1 nF)
Turn off fall time (C
LOAD
=1 nF)
Turn on first stage duration time
Min.
220
220
—
—
120
Typ.
440
440
24
7
200
3300
—
3300
—
—
Max. Units
660
660
—
—
280
4600
—
4600
—
—
Test Conditions
V
IN
= 0 & 1, V
S
= 0 V to 600 V
or 1200 V,
HOP shorted to HON, LOP
shorted to LON, Fig. 7
Fig. 8
V
HIN
= 1 V
V
DESAT
= 15 V, Fig. 10
V
LIN
= 1 V
V
DESAT
= 15 V, Fig. 10
Fig. 9
V
DS
=15 V, Fig. 9
DSH to HO soft shutdown propagation delay at HO
2000
turn on
DSH to HO soft shutdown propagation delay after
blanking
DSL to LO soft shutdown propagation delay at LO
turn on
DSL to LO soft shutdown propagation delay after
blanking
Soft shutdown minimum pulse width of desat
Soft shutdown duration period
DSH to SY_FLT propagation delay at HO turn on
DSH to SY_FLT propagation delay after blanking
DSL to SY_FLT propagation delay at LO turn on
DSL to SY_FLT propagation delay after blanking
DS blanking time at turn on
1050
2000
1050
1000
5700
—
1300
—
1050
—
9250 13500
ns
3600
—
3050
—
3000
—
—
—
—
—
V
HIN
= 1 V
V
DS
= 15 V, Fig. 10
V
LIN
= 1 V
V
DESAT
=15 V, Fig. 10
V
HIN
= V
LIN
= 1 V, V
DESAT
=15 V,
Fig. 10
t
SY_FLT,
DESAT2
t
SY_FLT
,
DESAT3
t
SY_FLT
,
DESAT4
t
BL
Deadtime/Delay Matching Characteristics
DT
MDT
PDM
Deadtime
Deadtime matching, MDT=DTH-DTL
Propagation delay matching,
Max (ton, toff) – Min (ton, toff)
—
—
—
330
—
—
—
75
75
Fig. 11
External DT = 0 s, Fig. 11
External DT > 500 ns, Fig. 7
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