IR3514
DATA SHEET
XPHASE3
TM
AMD HYBRID CONTROL IC
DESCRIPTION
The IR3514 Hybrid Control IC combined with
xPHASE3
Phase ICs provides a full featured and flexible
way to implement a complete AMD SVID or PVID power solution. It has the ability to independently control
both the VDD core and VDDNB auxiliary planes required by the CPU when operated in SVI (Serial VID
Interface) mode. The IR3514 can also receive Power Savings commands through the SVI serial bus and
communicate this information to the IR3507 or other Phase ICs with PSI input capabilities. When operated
in PVI (Parallel VID Interface) mode, the IR3514 controls the VDD core plane through 6 Parallel VID bits
and the VDDNB auxiliary plane power stage goes to high impedance. PVI/SVI selection is made by
sampling VID1 input upon Enable. The IR3514 interfaces with any number of Phase ICs each driving and
TM
monitoring a single phase. The
xPHASE3
architecture results in a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
TM
FEATURES
x
In SVI Mode (VID1=0 upon Enable)
o
2 converter outputs for the AMD processor VDD core and VDDNB auxiliary planes
o
AMD Serial VID interface independently programs both output voltages and operation
o
Both converter outputs boot to 2-bit “Boot” VID codes which are read and stored from the SVC
& SVD parallel inputs upon the assertion of the Enable input
o
PWROK input signal activates SVID after successful boot start-up
o
Both converter outputs can be independently turned on and off through SVID commands
o
Deassertion of PWROK prior to Enable causes the converter output to transition to the stored
Pre-PWROK VID codes
o
Connecting the PWROK input to VCCL disables SVID and implements VFIX mode with both
output voltages programmed via SVC & SVD parallel inputs per the 2 bit VFIX VID codes
o
PSI_L commands are forwarded to VDD core phase ICs
In PVI Mode (VID1=1 upon Enable)
o
Single converter control for VDD with the VDDNB power stage in a high impedance state
o
AMD 6 bit parallel VID programs the VDD regulation voltage
VRRDY monitors output voltages, VRRDY will deassert if any output voltage is out of spec
0.5% overall system set point accuracy
Programmable Dynamic VID Slew Rates
Programmable VID Offset (VDD output only)
Programmable output impedance (VDD output only)
High speed error amplifiers with wide bandwidths of 30MHz and fast slew rates of 12V/us
Remote sense amplifiers provide differential sensing and require less than 50uA bias current
Programmable per phase switching frequency of 250kHz to 1.5MHz
Daisy-chain digital phase timing provides accurate phase interleaving without external components
Hiccup over current protection with delay during normal operation
Central over voltage detection and communication to phase ICs through the IIN (ISHARE) pin
OVP disabled during dynamic VID down transitions to prevent false triggering
Detection and protection of open remote sense lines
Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO
Simplified VR Ready Output provides indication of proper operation and avoids false triggering
Thermally enhanced 40L MLPQ (6mm x 6mm) package
Over voltage signal to system with over voltage detection during powerup and normal operation
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x
x
x
x
x
x
x
x
x
x
x
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x
x
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Page 1 of 46
10/30/2007
IR3514
ORDERING INFORMATION
Device
IR3514MTRPBF
* IR3514MPBF
* Samples only
Package
40 Lead MLPQ (6 x 6 mm body)
40 Lead MLPQ (6 x 6 mm body)
Order Quantity
3000 per reel
100 piece strips
APPLICATION CIRCUIT
Figure 1 – IR3514 Application Circuit
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10/30/2007
IR3514
PIN DESCRIPTION
PIN#
1-3
4
5
PIN SYMBOL
VID0, VID5,
VID4
PWROK
ENABLE
PIN DESCRIPTION
PVI VID inputs (ignored in SVI mode). Requires an external pull-up bias and
should not be floated
SVI System wide Power Good signal and input to the IR3514. When asserted,
the IR3514 output voltage is programmed through the SVID interface protocol.
Connecting this pin to VCCL enables VFIX mode upon ENABLE. Ignored in PVI.
Enable input. A logic low applied to this pin puts the IC into fault mode. In SVI
mode, a logic high on the pin enables the converter and stores the SVC and
SVD input states to determine either a 2-bit BOOT or VFIX VID, depending on
the state of PWROK. Do not float this pin as the logic state will be undefined.
SVI mode output 2 average current information input from the phase IC(s). This
pin also communicates an over voltage condition to the output 2 phase ICs.
In SVI mode, programs the output 2 startup and over current protection delay
timing. Connect an external capacitor to LGND to program.
SVI mode output 2 reference voltage programmed by SVID commands. Connect
an external RC network to LGND to program the dynamic VID slew rate and
provide compensation for the internal buffer amplifier. In PVI mode, VDAC2 is
forced to 500mV.
Programs the SVI mode output 2 hiccup over-current threshold with an external
resistor to VDAC2 and an internal ROSC based current source. Over-current
protection can be disabled by setting an over-current threshold higher than the
maximum possible signal on the IIN2 pin from the phase ICs; do not exceed 5V
or float this pin as improper operation will occur.
SVI mode error amplifier 2 output. Held low in PVI mode.
No Connection
Inverting input to error amplifier 2.
Output 2 remote sense amplifier output.
Output 2 remote sense amplifier input. Kelvin at the load.
Output 2 remote sense amplifier input. Kelvin at the load return.
Output 1 remote sense amplifier input. Kelvin at the load return.
Output 1 remote sense amplifier input. Kelvin at the load.
Output 1 remote sense amplifier output.
Inverting input to error amplifier 1. Converter output voltage can be
programmed above the VDAC1 voltage by connecting an external resistor in
series with this pin. There is an ROSC based current sink on this pin.
No Connection
Error amplifier 1 output.
Programs the SVI mode output 1 hiccup over-current threshold with an external
resistor to VDAC1 and an internal ROSC based current source. Over-current
protection can be disabled by setting an over-current threshold higher than the
maximum possible signal on the IIN2 pin from the phase ICs, do not exceed 5V
or float this pin as improper operation will occur.
Output 1 reference voltage programmed by either SVID commands or parallel
VID bits. Connect an external RC network to LGND to program the dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
Programs the output 1 startup and over current protection delay timing. Connect
an external capacitor to LGND to program.
Output 1 average current information input from the phase IC(s). This pin also
communicates an over voltage condition to the output 1 phase ICs.
Buffered output of the IIN1 signal. Connect an external RC network to FB1 to
program converter output impedance.
10/30/2007
6
7
8
IIN2
SS/DEL2
VDAC2
9
OCSET2
10
11
12
13
14
15
16
17
18
19
20
21
22
EAOUT2
NC
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
NC
EAOUT1
OCSET1
23
24
25
26
VDAC1
SS/DEL1
IIN1
VDRP1
Page 3 of 46
IR3514
PIN DESCRIPTION CONTINUED:
PIN#
27
PIN SYMBOL
ROSC/OVP
PIN DESCRIPTION
Connect a resistor to LGND to program oscillator frequency and OCSET1,
OCSET2, FB1, VDAC1, and VDAC2 bias currents. Oscillator frequency equals
switching frequency per phase. The pin voltage is 0.6V during normal operation
and higher than 1.6V if over-voltage condition is detected.
Digital output to communicate PSI_L to Phase Ics.
Local ground for internal circuitry and IC substrate connection
No Connection
Clock output at switching frequency multiplied by phase number. Connect to
CLKIN pins of phase ICs.
Phase clock output at switching frequency per phase. Connect to PHSIN pin of
the first phase IC.
Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
Output of the voltage regulator, and power input for clock oscillator circuitry.
Connect a decoupling capacitor to LGND.
Non-inverting input of the voltage regulator error amplifier. Output voltage of the
regulator is programmed by a resistor divider connected to VCCL.
Output of the VCCL regulator error amplifier to control an external pass
transistor. The pin senses 12V power supply through a resistor.
Open collector output. It is asserted in SVI mode when both outputs are
regulated. It is asserted in PVI mode when VDD output is regulated. Connect
external pull-up.
In SVI mode, SVC (Serial VID Clock) is an input to IR3514 that is driven by an
open drain output of the processor. In PVI mode, this pin functions as the VID3
input. It requires an external pull-up and should not be floated.
In SVI mode, SVD (Serial VID Data) is a bidirectional signal that is an input and
open drain output for both the AMD processor and the IR3514. In PVI mode, this
pin functions as the VID2. It requires an external pull-up and should not be
floated.
This pin determines the control mode of the IR3514, either SVI or PVI. SVI
mode is selected if VID1=0 upon Enable. PVI mode is selected if VID1=1 upon
Enable. It requires an external pull-up and should not be floated.
28
29
30
31
32
33
34
35
36
37
38
39
PSI_L
LGND
NC
CLKOUT
PHSOUT
PHSIN
VCCL
VCCLFB
VCCLDRV
VRRDY
SVC/VID3
SVD/VID2
40
VID1
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10/30/2007
IR3514
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.
All voltages are absolute voltages referenced to the LGND pin.
Operating Junction Temperature……………..0 to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
o
Reflow Temperature…………………………….260 C
PIN #
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
40
PIN NAME
VID0
VID5
VID4
PWROK
ENABLE
IIN2
SS/DEL2
VDAC2
OCSET2
EAOUT2
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
EAOUT1
OCSET1
VDAC1
SS/DEL1
IIN1
VDRP1
ROSC/OVP
PSI_L
LGND
CLKOUT
PHSOUT
PHSIN
VCCL
VCCLFB
VCCLDRV
VRRDY
SVC/VID3
SVD/VID2
VID1
V
MAX
8V
8V
8V
8V
3.5V
8V
8V
3.5V
8V
8V
8V
8V
8V
1.0V
1.0V
8V
8V
8V
8V
8V
3.5V
8V
8V
8V
8V
8V
n/a
8V
8V
8V
8V
3.5V
10V
8V
8V
8V
8V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
n/a
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
I
SOURCE
1mA
1mA
1mA
1mA
1mA
5mA
1mA
1mA
1mA
25mA
1mA
5mA
5mA
5mA
5mA
5mA
5mA
1mA
25mA
1mA
1mA
1mA
5mA
35mA
1mA
1mA
20mA
100mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
I
SINK
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
10mA
1mA
25mA
1mA
1mA
1mA
1mA
25mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
10mA
1mA
100mA
10mA
1mA
20mA
1mA
50mA
20mA
1mA
10mA
1mA
o
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10/30/2007
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