MT90840
Distributed Hyperchannel Switch
Data Sheet
Features
•
Time slot interchange function between eight
pairs of ST-BUS/GCI/MVIP streams (512
channels) and parallel data port
Programmable data rates on the parallel port
(19.44, 16.384, or 6.480 Mbyte/s)
Programmable data rates on the serial port (2.048
Mbps, 4.096 Mbps or 8.192 Mbps)
Supports star and point-to-point connections, and
unidirectional or bidirectional ring topologies for
distributed systems
Input-to-output bypass function on the parallel
data port for use in add/drop applications
Provides elastic buffer at parallel input port in the
receive direction
Provides byte switching for up to 2430 channels
Per-channel direction control on the serial port
side
Per-channel message mode and high-impedance
control on both parallel and serial port sides
8-bit multiplexed microprocessor port compatible
with Intel and Motorola microcontrollers
•
•
•
•
•
Multiple Pages of 512 Position
TX Path Data Memory
16
2430 Position
TX Path
Connection Memory
8
Conver-
ters
June 2007
Ordering Information
MT90840AL1
MT90840AP1
MT90840APR1
100 Pin MQFP*
84 Pin PLCC*
84 Pin PLCC*
*Pb Free Matte Tin
-40°C to +85°C
Trays
Tubes
Tape & Reel
•
•
•
•
•
Guarantees frame integrity when switching nX64
wideband channels such as ISDN H0 channel
Provides external control lines allowing fast
parallel interface to be shared with other devices
•
•
•
•
•
•
Applications
•
Bridging ST-BUS/MVIP buses to high speed Time
Division Multiplexed backplanes at SONET rates
(STS-1, STS-3)
High speed isochronous backbones for distributed
PBX and LAN systems
Switch platforms of up to 2430 channels with
guaranteed frame integrity for wideband channels
Serial bus control and monitoring
Data multiplexing
High speed communications interface
8
Serial
to
Parallel
&
Bidirectional
I/O
Driver
STi0
STi7
PDo0
PDo7
CTo0-3
PDi0
PDi7
8
Output
Mux &
Drivers
4
8
8
Parallel
to
Serial
Multiple Pages of 2430-Byte
RX Path Data Memory
15
Bidirectional
I/O
Driver
STo0
STo7
PCKR
PCKT
RES
PPFRi
PPFTi/o
F0i/o
Timing
Control
Unit
512 Position
RX Path
Connection Memory
JTAG
5
TEST
Pins
CPU Interface
Internal
Registers
8
8
VSS
R/W\WR
AD0-7
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2007, Zarlink Semiconductor Inc. All Rights Reserved.
AS/ALE
C4/8R1
C4/8R2
SPCKo
DS/RD
DTA
VDD
IRQ
CS
MT90840
Change Summary
Data Sheet
Changes from April 2006 to April 2007. Page, section, figure and table numbers refer to this current issue.
Page
1
Item
Ordering Information Box
Change
Removed part numbers MT90840AL and MT90840AP from
ordering information.
2
Zarlink Semiconductor Inc.
MT90840
VSS
NC
IC
RES
IRQ
DTA
CS
AS/ALE
DS/RD
VDD
VSS
R/W
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VDD
Data Sheet
46
48
34
36
VSS
32
38
44
50
VDD
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
C4/8R1
F0i/o
C4/8R2
VSS
VDD
NC
NC
CTo3
CTo2
CTo1
CTo0
84
82
80
78
14
16
18
20
22
24
26
28
30
40
42
10
84 PIN PLCC
NC
NC
NC
NC
VDD
NC
PDo7
VDD
PDo6
VSS
PDo5
CTo0
PDo4
CTo1
PDo3
CTo2
PDo2
CTo3
PDo1
VDD
PDo0
VSS
PPFTi/o
C4/8R2
VSS
F0i/o
VDD
C4/8R1
PDi7
STi7
PDi6
STi6
PDi5
STi5
STi4
PDi4
STi3
PDi3
STi2
PDi2
STi1
PDi1
STi0
PDi0
VDD
VSS
VSS
NC
NC
NC
NC
80
82
84
46
86
44
88
42
90
92
94
36
96
34
98
100 2
4
6
8
10
12
14
16
18
20
22
24
26
28
32
30
100 PIN PQFP
40
38
78
76
74
72
70
68
66
64
62
60
58
56
54
52 50
48
52
76
12
74
72
70
68
66
64
62
60
58
56
54
VSS
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
SPCKo
VSS
VDD
TDO
TMS
TCK
TRST
TDI
PPFRi
PCKT
PCKR
VDD
8
6
4
2
PDo7
PDo6
PDo5
PDo4
PDo3
PDo2
PDo1
PDo0
PPFTi/o
VSS
VDD
PDi7
PDi6
PDi5
PDi4
PDi3
PDi2
PDi1
PDi0
VSS
NC
IC
RES
IRQ
DTA
CS
AS/ALE
DS
/
RD
VDD
VSS
R/W
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NC
NC
NC
NC
NC
VDD
PCKR
PCKT
PPFRi
TDI
TRST
TCK
TMS
TDO
VDD
VSS
SPCKo
STo7
STo6
STo5
STo4
STo3
STo2
STo1
STo0
VSS
VDD
NC
NC
NC
NC
Figure 2 - Pin Connections
3
Zarlink Semiconductor Inc.
MT90840
Pin Description
Pin #
84
3
100
43
Name
DS/RD
Description
Data Sheet
Data Strobe/Read (Input).
In Motorola multiplexed-bus mode this pin is DS, an
active high input which works with CS to enable read and write operation. In
Intel/National multiplexed-bus mode this pin is RD, an active low input which
enables a read-cycle and configures the data bus lines (AD0-AD7) as outputs.
Address Strobe / Address Latch Enable (Input).
Falling edge is used to sample
address into the Address Latch circuit.
Chip Select (Input).
Active low input enabling a microprocessor read or write of
control or status registers.
Data Acknowledgment (Active Low Output).
Indicates that a data bus transfer is
complete. When the bus cycle ends, this pin drives HIGH and then tri-states,
allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is
required to hold a HIGH level when the pin is tri-stated. Note that CPU read/writes
from/to the Data and Connection memories occur on the serial or parallel port
clock edges, and DTA will not change state if the clock is halted.
Interrupt Request (Active High Output).
Output indicates that the MT90840 has
detected an alarm condition. The indication of the specific condition can be read in
the ALS (Alarm Status) Register. The CPU should read ALS, identify the source for
the interrupt and then rewrite the mask bits to re-enable the IRQ signal.
RESET (Schmitt Input).
Asynchronous device reset. A logic-high signal should be
applied during power-up to bring the MT90840 internal circuitry to a defined state.
Serial and parallel TDM outputs (STo0-7, STi0-7, and PDo0-7) are held in high-
impedance state after reset until programmed otherwise. This input must be held
low during normal operation.
Internal Connection. The user must connect this pin to V
SS
. This pin must remain
low for the MT90840 to function normally, and to comply with IEEE 1149 (JTAG)
boundary scan requirements. This pin is pulled low internally when not driven.
No Connection.
4
5
6
44
45
46
AS/ALE
CS
DTA
7
47
IRQ
8
48
RES
9
49
IC
10,
26,
27
13-20
1-4,
27-31
50-54
76-80
57-64
NC
STi0-STi7
Serial Inputs 0 to 7 (Bidirectional).
Serial TDM data-streams at 2.048, 4.096 or
8.192 Mbps, with 32, 64 or 128 channels respectively per stream. For 2.048 and
4.096 Mbps applications, streams STi0-STi7 can be used, while for 8.192 Mbps,
only streams STi0-STi3 are used (512 channel limit). These eight bidirectional
lines can be programmed as inputs (default) or outputs on a per-channel basis.
4
Zarlink Semiconductor Inc.
MT90840
Pin Description (continued)
Pin #
84
21
100
65
Name
C4/8R1
Description
Data Sheet
Serial Clock Reference Input 1.
When enabled by the C4/8R bit (high) in the TIM
Register, this input receives the 4.096 or 8.192 MHz serial port clock reference. If
the C4/8R bit is set low, or if the INTCLK bit is set high, this input is ignored by the
MT90840.
In Timing Mode 1 (TM1), or at 8.192 MHz, the C4/8 input is used directly to shift
data in and out of the serial port.
In Timing Mode 2 (TM2) at 4.096 MHz, the C4 input from an external clock source
(e.g. a PLL locked to an 8 kHz reference) is phase-corrected by the MT90840, and
used to generate the serial port SPCKo and F0 outputs.
In Timing Modes 3 and 4 (TM3 and TM4) this input is not used.
For more details on the use of this signal, see the description of Timing Mode 1
and Timing Mode 2.
22
66
F0i/o
Serial Port Frame Synchronization (Bidirectional). This 8 kHz frame pulse signal
indicates the TDM 125
µsec
frame boundary on the serial data port. This pin is
compatible with both ST-BUS/MVIP and GCI formatted framing signals.
In TM1 this pin is an input, and the MT90840 senses the polarity of this frame
pulse and automatically adapts the serial data port timing to the applicable format
(ST-BUS or GCI).
In TM2 with SFDI =1 this signal is an input, and its expected format is determined
by the SPFP bit in the GPM Register.
In TM2 (with SFDI =0), and in TM3, this signal is an output, generated from the
internal timing and synchronized to the SPCKo output clock. The polarity of the F0
pulse is determined by the SPFP bit in the GPM Register.
In TM4 this pin is not used.
23
67
C4/8R2
C4/8R2 Serial Clock Reference Input 2.
When enabled by the C4/8R bit (low) in
the TIM Register, this input receives the 4.096 or 8.192 MHz serial port clock
reference. If the C4/8R bit is set high, or if the INTCLK bit is set high, this input is
ignored by the MT90840. (See pin description for C4/8R1.)
External Control Lines 3 to 0 (Output).
Output signals generated from the
MT90840 Transmit Path Connection Memory (TPCM). The four serial CTo output
lines represent the contents of the four CT bits in the TPCM, and are clocked at the
parallel port rate (up to 19.44 MHz). See Per-Channel Functions section.
Parallel Data Output Port 7 to 0 (Output).
These eight outputs carry the parallel
port data bytes in the transmit direction and operate at data rates up to
19.44 Mbyte/s.
28-31
70-73
CTo3-
CTo0
34-41
81-88
PDo7-
PDo0
5
Zarlink Semiconductor Inc.
FPGA/CPLD
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