74VHC540FT,74VHC541FT
CMOS Digital Integrated Circuits
Silicon Monolithic
74VHC540FT,74VHC541FT
1. Functional Description
• Octal Bus Buffer
74VHC540FT: INVERTED, 3-STATE OUTPUTS
74VHC541FT: NON-INVERTED, 3-STATE OUTPUTS
2. General
The 74VHC540FT/74VHC541FT are advanced high speed CMOS OCTAL BUS BUFFERs fabricated with silicon
gate C
2
MOS technology.
They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS
low power dissipation.
The 74VHC540FT is an inverting type, and the 74VHC541FT is a non-inverting type.
When either G1 or G2 are high, the terminal outputs are in the high-impedance state.
An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply
voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages
3. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
High speed: Propagation delay time = 3.7 ns (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 4
µA
(max) at T
a
= 25
High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
Power down protection is provided on all inputs.
Balanced propagation delays: t
PLH
≈
t
PHL
Wide operating voltage range: V
CC(opr)
= 2 V to 5.5 V
Low noise: V
OLP
= 1.0 V (max)
Pin and function compatible with 74 series (74AC/HC/AHC/LV etc.) 540 or 541 type.
4. Packaging
TSSOP20B
Start of commercial production
1
2013-03
2014-06-03
Rev.3.0
74VHC540FT,74VHC541FT
5. Pin Assignment
74VHC540FT
74VHC541FT
6. Marking
74VHC540FT
74VHC541FT
7. IEC Logic Symbol
74VHC540FT
74VHC541FT
2
2014-06-03
Rev.3.0
74VHC540FT,74VHC541FT
8. Truth Table
Input G1
H
X
L
L
Input G2
X
H
L
L
Input A
n
X
X
H
L
Output Y
n
Z
Z
H
L
Output Y
n
Z
Z
L
H
X:
Z:
Yn:
Yn:
Don't care
High impedance
74VHC541FT
74VHC540FT
9. Absolute Maximum Ratings (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Input diode current
Output diode current
Output current
V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
-0.5 to 7.0
-0.5 to 7.0
-0.5 to V
CC
+ 0.5
-20
±20
±25
±75
180
-65 to 150
mW
mA
Unit
V
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
10. Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall times
Symbol
V
CC
V
IN
V
OUT
T
opr
dt/dv
V
CC
= 3.3
±
0.3 V
V
CC
= 5
±
0.5 V
Test Condition
Rating
2.0 to 5.5
0 to 5.5
0 to V
CC
-40 to 85
0 to 100
0 to 20
ns/V
Unit
V
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs and bus inputs must be tied to either V
CC
or GND.
3
2014-06-03
Rev.3.0
74VHC540FT,74VHC541FT
11. Electrical Characteristics
11.1. DC Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
High-level input voltage
Low-level input voltage
High-level output voltage
Symbol
V
IH
V
IL
V
OH
Test Condition
V
CC
(V)
2.0
3.0 to 5.5
2.0
3.0 to 5.5
V
IN
= V
IH
or V
IL
I
OH
= -50
µA
2.0
3.0
4.5
I
OH
= -4 mA
I
OH
= -8 mA
Low-level output voltage
V
OL
V
IN
= V
IH
or V
IL
I
OL
= 50
µA
3.0
4.5
2.0
3.0
4.5
I
OL
= 4 mA
I
OL
= 8 mA
3-state output OFF-state
leakage current
Input leakage current
Quiescent supply current
I
OZ
I
IN
I
CC
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
3.0
4.5
5.5
0 to 5.5
5.5
Min
1.50
V
CC
×
0.7
1.9
2.9
4.4
2.58
3.94
Typ.
2.0
3.0
4.5
0.0
0.0
0.0
Max
0.50
V
CC
×
0.3
0.1
0.1
0.1
0.36
0.36
±0.25
±0.1
4.0
µA
Unit
V
11.2. DC Characteristics (Unless otherwise specified, T
a
= -40 to 85
)
Characteristics
High-level input voltage
Low-level input voltage
High-level output voltage
Symbol
V
IH
V
IL
V
OH
Test Condition
V
CC
(V)
2.0
3.0 to 5.5
2.0
3.0 to 5.5
V
IN
= V
IH
or V
IL
I
OH
= -50
µA
2.0
3.0
4.5
I
OH
= -4 mA
I
OH
= -8 mA
Low-level output voltage
V
OL
V
IN
= V
IH
or V
IL
I
OL
= 50
µA
3.0
4.5
2.0
3.0
4.5
I
OL
= 4 mA
I
OL
= 8 mA
3-state output OFF-state
leakage current
Input leakage current
Quiescent supply current
I
OZ
I
IN
I
CC
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
3.0
4.5
5.5
0 to 5.5
5.5
Min
1.50
V
CC
×
0.7
1.9
2.9
4.4
2.48
3.80
Max
0.50
V
CC
×
0.3
0.1
0.1
0.1
0.44
0.44
±2.50
±1.0
40.0
µA
Unit
V
4
2014-06-03
Rev.3.0
74VHC540FT,74VHC541FT
11.3. AC Characteristics (Unless otherwise specified, T
a
= 25
, Input: t
r
= t
f
= 3 ns)
Characteristics
Propagation delay time
Part Number
74VHC540FT
Symbol
t
PLH
,t
PHL
Note
Test
Condition
V
CC
(V)
3.3
±
0.3
5.0
±
0.5
74VHC541FT
t
PLH
,t
PHL
3.3
±
0.3
5.0
±
0.5
3-state output enable time
t
PZL
,t
PZH
R
L
= 1 kΩ 3.3
±
0.3
5.0
±
0.5
3-state output disable time
Output skew
Input capacitance
Output capacitance
Power dissipation
capacitance
74VHC540FT
74VHC541FT
t
PLZ
,t
PHZ
t
osLH
,t
osHL
(Note 1)
C
IN
C
OUT
C
PD
(Note 2)
R
L
= 1 kΩ
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
C
L
(pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
50
50
Min
Typ.
4.8
7.3
3.7
5.2
5.0
7.5
3.5
5.0
6.8
9.3
4.7
6.2
11.2
6.0
4
6
17
18
Max
7.0
10.5
5.0
7.0
7.0
10.5
5.0
7.0
10.5
14.0
7.0
9.2
15.4
8.8
1.5
1.0
10
pF
Unit
ns
Note 1: Parameter guaranteed by design. (t
osLH
= |t
PLHm
- t
PLHn
|, t
osHL
= |t
PHLm
- t
PHLn
|)
Note 2: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load. Average operating current can be obtained by the equation.
I
CC(opr)
= C
PD
×
V
CC
×
f
IN
+ I
CC
/8 (per bit)
5
2014-06-03
Rev.3.0
_pdf/pg_0001.png)
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界_pdf/1.png)
_pdf/2.png)
_pdf/3.png)
_pdf/4.png)
_pdf/5.png)
_pdf/pg_0002.png)
_pdf/pg_0003.png)
_pdf/pg_0004.png)
_pdf/pg_0005.png)
