MT90823
3 V Large Digital Switch
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
•
•
2,048
×
2,048 channel non-blocking switching at
8.192 Mb/s
Per-channel variable or constant throughput
delay
Automatic identification of ST-BUS/GCI interfaces
Accept ST-BUS streams of 2.048, 4.096 or
8.192 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel message mode
Control interface compatible to Motorola non-
multiplexed CPUs
Connection memory block programming
3.3 V local I/O with 5 V tolerant inputs and TTL-
compatible outputs
IEEE-1149.1 (JTAG) Test Port
Ordering Information
MT90823AP
84 Pin PLCC
Tubes
MT90823AL
100 Pin MQFP
Trays
MT90823AB
100 Pin LQFP
Trays
MT90823AG
120 Pin BGA
Trays
MT90823AB1 100 Pin LQFP*
Trays
MT90823AP1 84 Pin PLCC*
Tubes
MT90823AL1
100 Pin MQFP*
Trays
MT90823AG2 120 Pin BGA**
Trays
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40°C to +85°C
January 2006
Applications
•
•
•
•
•
•
Medium and large switching platforms
CTI application
Voice/data multiplexer
Digital cross connects
ST-BUS/GCI interface functions
Support IEEE 802.9a standard
V
DD
V
SS
TMS
TDI
TDO
TCK
TRST
IC
RESET
ODE
Test Port
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
Serial
to
Parallel
Converter
Loopback
Parallel
Multiple Buffer
Data Memory
Output
MUX
to
Serial
Converter
Internal
Registers
Connection
Memory
Timing
Unit
Microprocessor Interface
CLK
F0i
FE/ WFPS
HCLK
AS/ IM DS/ CS R/W
ALE
RD
/WR
A7-A0 DTA D15-D8/ CSTo
AD7-AD0
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MT90823
Description
Data Sheet
The MT90823 Large Digital Switch has a non-blocking switch capacity of: 2,048 x 2,048 channels at a serial bit rate
of 8.192 Mb/s; 1,024 x 1,024 channels at 4.096 Mb/s; and 512 x 512 channels at 2.048 Mb/s. The device has many
features that are programmable on a per stream or per channel basis, including message mode, input offset delay
and high impedance output control.
Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice
channel and concatenated data channels.
In addition, the input stream can be individually calibrated for input frame offset using a dedicated pin.
2
Zarlink Semiconductor Inc.
MT90823
VSS
STo15
STo14
STo13
STo12
STo11
STo10
STo9
STo8
VDD
VSS
STo7
STo6
STo5
STo4
STo3
STo2
STo1
STo0
ODE
VSS
Data Sheet
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
F0i
FE/HCLK
VSS
CLK
VDD
10
13
15
17
19
21
23
25
27
29
31
34
8
6
4
2
84
82
80
78
76
73
71
69
67
84 PIN PLCC
65
63
61
59
57
55
36
38
40
42
44
46
48
50
52
CSTo
DTA
D15
D14
D13
D12
D11
D10
D9
D8
VSS
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
NC
NC
NC
NC
VSS
STo15
STo14
STo13
STo12
STo11
STo10
STo9
STo8
VDD
VSS
STo7
STo6
STo5
STo4
STo3
STo2
STo1
STo0
ODE
VSS
CSTo
NC
NC
NC
NC
80
82
48
84
46
86
44
88
90
92
94
36
96
34
98
99
2
4
6
8
10
12
14
16
18
20
22
24
26
28
32
30
42
40
38
78
76
74
72
70
68
66
64
62
60
58
56
54
52 50
TMS
TDI
TDO
TCK
TRST
IC
RESET
WFPS
A0
A1
A2
A3
A4
A5
A6
A7
DS/RD
R/W/RW
CS
AS/ALE
IM
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
F0i
FE/HCLK
VSS
CLK
100 PIN MQFP
(14mm x 20mm x 2.75mm)
DTA
D15
D14
D13
D12
D11
D10
D9
D8
VSS
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
NC
NC
NC
NC
VDD
TMS
TDI
TDO
TCK
TRST
IC
RESET
WFPS
A0
A1
A2
A3
A4
A5
A6
A7
DS/RD
R/W/RW
CS
AS/ALE
IM
NC
NC
NC
NC
Figure 2 - PLCC and MQFP Pin Connections
3
Zarlink Semiconductor Inc.
MT90823
1
A
B
C
D
E
F
G
H
J
K
STi14 STi15 VDD
L
VSS
F0i FE/HCLK
M
VSS
N
CLK
TMS TDO TRST RESETA0
A2
A3
A5
A7
DS/RD CS
IM
VSS
TDI
TCK IC
WFPS A1
A4
A6
AS/ALE
R/W/RW
VSS
VSS
VDD VSS
VDD VSS
VDD VSS VDD VSS AD0
AD1
VDD AD2
AD3
1
2
3
4
5
6
7
8
9
10
11
12
13
Data Sheet
VSS
VSS
STi0
STi2
STi4
STi6
STi8
VSS
VSS
STo14 STo12STo10 STo9 STo7 STo5 STo4 STo2 STo0 VSS
STo15 STo13STo11 STo8 VSS
VDD VSS
VDD VSS
STo6 STo3 STo1 ODE VSS
VDD VSS VDD VSS DTA
VDD D14
VSS D12
VSS
VSS
CSTo
D15
D13
D11
D9
AD7
AD5
STi1 VSS
STi3 VDD
STi5 VSS
TOP VIEW
STi7 VDD
VDD D10
PBGA
STi9 VSS
STi10 STi11 VDD
STi12 STi13 VSS
(23mm x 23mm x 2.13mm)
(Ball Pitch = 1.5mm)
VSS D8
VDD AD6
VSS AD4
1
- A1 corner is identified by metallized markings.
NC
NC
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
F0i
FE/HCLK
VSS
CLK
VDD
NC
NC
76
78
80
82
84
86
88
90
92
94
96
98
100
2
4
6
8
10
12
14
16
18
20
22
24
NC
NC
VSS
STo15
STo14
STo13
STo12
STo11
STo10
STo9
STo8
VDD
VSS
STo7
STo6
STo5
STo4
STo3
STo2
STo1
STo0
ODE
VSS
NC
NC
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
100 PIN LQFP
(14mm x 14mm x 1.4mm)
(Pin Pitch = 0.50mm)
40
38
36
34
32
30
28
26
NC
NC
CSTo
DTA
D15
D14
D13
D12
D11
D10
D9
D8
VSS
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
NC
NC
NC
NC
TMS
TDI
TDO
TCK
TRST
IC
RESET
WFPS
A0
A1
A2
A3
A4
A5
A6
A7
DS/RD
R/W/RW
CS
AS/ALE
IM
NC
NC
Figure 3 - PBGA and LQFP Pin Connections
4
Zarlink Semiconductor Inc.
MT90823
Pin Description
Pin #
84
100
PLCC MQFP
1, 11, 31, 41,
30, 54 56, 66,
64, 75 76, 99
100
LQFP
28,
38,
53,
63,
73,
96
37,
64,98
120
BGA
A1,A2,A12,A13,
B1,B2,B7,B12,
B13,C3,C5,C7,
C9,C11,E3,E11
G3,G11,J3,J11,
L3,L5,L7,L9,L11,
M1,M2,M12,M13
C4,C6,C8,C10,
D3,D11,F3,F11,
H3,H11,K3,K11,
L4,L6,L8,L10
B6,A6,A5,B5,A4,
B4,A3,B3
Name
Description
Data Sheet
V
SS
Ground.
2, 32,
63
5, 40,
67
V
DD
+3.3 Volt Power Supply.
3 - 10
68-75
65 -
72
STo8 - 15
ST-BUS Output 8 to 15 (5 V Tolerant Three-state
Outputs):
Serial data Output stream. These streams
may have data rates of 2.048, 4.096 or 8.192 Mb/s,
depending upon the value programmed at bits DR0 - 1
in the IMS register.
STi0 - 15
ST-BUS Input 0 to 15 (5 V Tolerant Inputs):
Serial
data input stream. These streams may have data rates
of 2.048, 4.096 or 8.192 Mb/s, depending upon the
value programmed at bits DR0 - 1 in the IMS register.
Frame Pulse (5 V Tolerant Input):
When the WFPS
pin is low, this input accepts and automatically
identifies frame synchronization signals formatted
according to ST-BUS and GCI specifications. When the
WFPS pin is high, this pin accepts a negative frame
pulse which conforms to WFPS formats.
12 -
27
81-96
78 -
93
C1,C2,D1,D2,E1,
E2,F1,F2,G1,G2,
H1,H2,J1,J2,K1,
K2
L1
28
97
94
F0i
29
98
95
L2
FE/HCLK
Frame Evaluation / HCLK Clock (5 V Tolerant
Input):
When the WFPS pin is low, this pin is the frame
measurement input. When the WFPS pin is high, the
HCLK (4.096MHz clock) is required for frame
alignment in the wide frame pulse (WFP) mode.
CLK
Clock (5 V Tolerant Input):
Serial clock for shifting
data in/out on the serial streams (STi/o 0 - 15).
Depending upon the value programmed at bits DR0 - 1
in the IMS register, this input accepts a 4.096, 8.192 or
16.384 MHz clock.
Test Mode Select (3.3 V Input with internal pull-up):
JTAG signal that controls the TAP controller state
transitions.
Test Serial Data In (3.3 V Tolerant Input with internal
pull-up):
JTAG serial test instructions and data are
shifted in on this pin.
31
100
97
N1
33
6
3
N2
TMS
34
7
4
M3
TDI
5
Zarlink Semiconductor Inc.
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