74VHCT573AFT
CMOS Digital Integrated Circuits
Silicon Monolithic
74VHCT573AFT
1. Functional Description
•
Octal D-Type Latch with 3-State Outputs
2. General
The 74VHCT573A is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with
silicon gateC
2
MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS
low power dissipation.
This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE).When the OE
input is high, the eight outputs are in a high impedance state.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output
(Note)
pins without
regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/
output voltages such as battery back up, hot board insertion, etc.
Note: Output in off-state
3. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
High speed: Propagation delay time = 7.7 ns (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 4
µA
(max) at T
a
= 25
Compatible with TTL inputs: V
IL
= 0.8 V (max)
V
IH
= 2.0 V (min)
Power down protection is provided on all inputs and outputs.
Balanced propagation delays: t
PLH
≈
t
PHL
Low noise: V
OLP
= 1.5 V (max)
Pin and function compatible with the 74 series
(74ACT/HCT/AHCT etc.) 573 type.
4. Packaging
TSSOP20B
Start of commercial production
1
2014-04
2014-06-03
Rev.2.0
74VHCT573AFT
5. Pin Assignment
6. Marking
7. IEC Logic Symbol
2
2014-06-03
Rev.2.0
74VHCT573AFT
8. Truth Table
INPUT
OE
H
L
L
L
INPUT
LE
X
L
H
H
INPUT
D
X
X
L
H
OUTPUT
Z
Q
n
L
H
X:
Z:
Qn:
Don't care
High impedance
Q outputs are latched at the time when
the LE input is taken to a low logic level.
9. System Diagram
3
2014-06-03
Rev.2.0
74VHCT573AFT
10. Absolute Maximum Ratings (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Input diode current
Output diode current
Output current
V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
(Note3)
(Note1)
(Note2)
Note
Rating
-0.5 to 7.0
-0.5 to 7.0
-0.5 to 7.0
-0.5 to V
CC
+ 0.5
-20
±20
±25
±75
180
-65 to 150
mA
mA
mA
mA
mW
Unit
V
V
V
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note1: Output in off-state
Note2: High or low state. I
OUT
absolute maximum rating must be observed.
Note3: V
OUT
< GND, V
OUT
> V
CC
11. Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall times
Symbol
V
CC
V
IN
V
OUT
T
opr
dt/dv
(Note1)
(Note2)
Note
Rating
4.5 to 5.5
0 to 5.5
0 to 5.5
0 to V
CC
-40 to 85
0 to 20
ns/V
Unit
V
V
V
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs and bus inputs must be tied to either V
CC
or GND.
Note1: V
CC
= 0 V
Note2: High or low state
4
2014-06-03
Rev.2.0
74VHCT573AFT
12. Electrical Characteristics
12.1. DC Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
3-state output OFF-state
leakage current
Input leakage current
Quiescent supply current
Quiescent supply current
Output leakage current
Symbol
V
IH
V
IL
V
OH
V
OL
I
OZ
I
IN
I
CC
I
CCT
I
OPD
Test Condition
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
Per input: V
IN
= 3.4 V
Other input: V
CC
or GND
V
OUT
= 5.5 V
I
OH
= -50
µA
I
OH
= -8mA
I
OL
= 50
µA
I
OL
= 8mA
V
CC
(V)
4.5 to 5.5
4.5 to 5.5
4.5
4.5
4.5
4.5
5.5
0 to 5.5
5.5
5.5
0
Min
2.0
4.40
3.94
Typ.
4.50
0.0
Max
0.8
0.1
0.36
±0.25
±0.1
4.0
1.35
0.5
µA
µA
µA
mA
µA
V
Unit
V
V
V
12.2. DC Characteristics (Unless otherwise specified, T
a
= -40 to 85
)
Characteristics
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
3-state output OFF-state
leakage current
Input leakage current
Quiescent supply current
Quiescent supply current
Output leakage current
Symbol
V
IH
V
IL
V
OH
V
OL
I
OZ
I
IN
I
CC
I
CCT
I
OPD
Test Condition
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
Per input: V
IN
= 3.4 V
Other input: V
CC
or GND
V
OUT
= 5.5 V
I
OH
= -50
µA
I
OH
= -8 mA
I
OL
= 50
µA
I
OL
= 8 mA
V
CC
(V)
4.5 to 5.5
4.5 to 5.5
4.5
4.5
4.5
4.5
5.5
0 to 5.5
5.5
5.5
0
Min
2.0
4.40
3.80
Max
0.8
0.1
0.44
±2.50
±1.0
40.0
1.50
5.0
µA
µA
µA
mA
µA
V
Unit
V
V
V
25
12.3. Timing Requirements (Unless otherwise specified, T
a
= 25
, Input: t
r
= t
f
= 3 ns)
Characteristics
Minimum pulse width (LE)
Minimum setup time
Minimum hold time
Symbol
t
w(H)
t
S
t
h
V
CC
(V)
5.0
±
0.5
5.0
±
0.5
5.0
±
0.5
Typ.
Limit
6.5
1.5
3.5
Unit
ns
ns
ns
12.4. Timing Requirements
(Unless otherwise specified, T
a
= -40 to 85
, Input: t
r
= t
f
= 3 ns)
85
Characteristics
Minimum pulse width (LE)
Minimum setup time
Minimum hold time
Symbol
t
w(H)
t
S
t
h
V
CC
(V)
5.0
±
0.5
5.0
±
0.5
5.0
±
0.5
Limit
8.5
1.5
3.5
Unit
ns
ns
ns
5
2014-06-03
Rev.2.0
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