MT9196
Integrated Digital Phone Circuit (IDPC)
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
Programmable m-Law/A-Law CODEC and
Filters
Programmable CCITT (G.711)/sign-magnitude
coding
Programmable transmit, receive and side-tone
gains
Digital DTMF and single tone generation
Fully differential interface to handset
transducers
Auxiliary analog interface
Interface to ST-BUS/SSI (compatible with GCI)
Serial microport control
Single 5 volt supply, low power operation
Anti-howl circuit for group listening
speakerphone applications
The MT9196 Integrated Digital Phone Circuit (IDPC) is
designed for use in digital phone products. The device
incorporates a built-in Filter/Codec, digital gain pads,
DTMF generator and tone ringer. Complete telephony
interfaces are provided for connecting to handset and
speakerphone transducers. Internal register access is
provided through a serial microport compatible with
various industry standard micro-controllers.
The device is fabricated in Zarlink's ISO
2
-CMOS
technology ensuring low power consumption and high
reliability.
Filter/Codec Gain
Encoder
Decoder
7dB
-7dB
Transducer
Interface
January 2006
ISO
2
-CMOS
Ordering Information
MT9196AP
28 Pin PLCC
Tubes
MT9196AE
28 Pin PDIP
Tubes
MT9196AS
28 Pin SOIC
Tubes
MT9196ASR
28 Pin SOIC
Tape &
MT9196APR
28 Pin PLCC
Tape &
MT9196AE1
28 Pin PDIP*
Tubes
MT9196APR1 28 Pin PLCC*
Tape &
MT9196AP1
28 Pin PLCC*
Tubes
MT9196AS1
28 Pin SOIC*
Tubes
MT9196ASR1 28 Pin SOIC*
Tape &
*Pb Free Matte Tin
-40°C to +85°C
Reel
Reel
Reel
Reel
Description
Applications
•
•
•
Digital telephone sets
Wireless telephones
Local area communications stations
Digital Gain & Tone Generator
VSSD
VDD
VSSA
VSS SPKR
VBias
VRef
21/ - 24dB
∆3.0dB
Tx & Rx
AUXin
AUXout
MIC +
M-
M+
HSPKR +
HSPKR -
Din
Timing
Dout
STB/F0i
CLOCKin
Serial Microport
XSTL2
IC
IRQ
CS
DATA1
DATA2
SCLK
Flexible
Digital
Interface
SPKR +
SPKR -
ST-BUS
C&D
Channels
WD
PWRST
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1995-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT9196
Data Sheet
M+
M-
VSSA
MIC+
AUXin
VRef
VBias
PWRST
IC
VSSD
CS
SCLK
DATA1
DATA2
4 3 2 1 28 27 26
5
25
24
6
7
23
22
8
21
9
20
10
11
19
12 13 14 15 16 17 18
AUXout
VSS SPKR
SPKR+
SPKR-
HSPKR+
HSPKR-
VDD
WD
IRQ
Dout
Din
STB/F0i
CLOCKin
XSTAL2
M-
M+
VBias
VRef
PWRST
IC
VSSD
CS
SCLK
DATA1
DATA2
WD
IRQ
Dout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSSA
MIC+
AUXin
AUXout
VSS SPKR
SPKR+
SPKR-
HSPKR+
HSPKR-
VDD
XSTAL2
CLOCKin
STB/F0i
Din
28 PIN PLCC
28 PIN SOIC/PDIP
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
Name
M-
M+
V
Bias
V
Ref
PWRST
IC
V
SSD
CS
SCLK
DATA1
Description
Inverting Microphone (Input).
Inverting input to microphone amplifier from the handset
microphone.
Non-Inverting Microphone (Input).
Non-inverting input to microphone amplifier from the
handset microphone.
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external amplifiers.
Connect 0.1
µF
capacitor to V
SSA
.
Reference voltage for codec (Output).
Nominally [(V
DD
/2)-1.5] volts. Used internally.
Connect 0.1
µF
capacitor to V
SSA
.
Power-up Reset (Input).
CMOS compatible input with Schmitt Trigger (active low).
Internal Connection.
Tie externally to V
SS
for normal operation.
Digital Ground.
Nominally 0 volts.
Chip Select (Input).
This input signal is used to select the device for microport data
transfers. Active low. TTL level compatible.
Serial Port Synchronous Clock (Input).
Data clock for microport. TTL level compatible.
Bidirectional Serial Data.
Port for microprocessor serial data transfer. In Motorola/National
mode of operation, this pin becomes the data transmit pin only and data receive is
performed on the DATA2 pin. TTL level compatible input levels.
Serial Data Receive.
In Motorola/National mode of operation, this pin is used for data
receive to the IDPC. In Intel mode, serial data transmit and receive are performed on the
DATA1 pin and DATA2 is disconnected. Input level TTL compatible.
Watchdog (Output).
Watchdog timer output. Active high.
Interrupt Request (Open Drain Output).
Low true interrupt output to microcontroller.
11
DATA2
12
13
WD
IRQ
2
Zarlink Semiconductor Inc.
MT9196
Pin Description (continued)
Pin #
14
Name
D
out
Description
Data Sheet
Data Output.
A tri-state digital output for 8 bit wide channel data being sent to the Layer 1
device. Data is shifted out via this pin concurrent with the rising edge of BCL during the
timeslot defined by STB, or according to standard ST-BUS timing.
Data Input.
A digital input for 8 bit wide channel data received from the Layer 1 device. Data
is sampled on the falling edge of BCL during the timeslot defined by STB, or according to
standard ST-BUS timing. Input level is CMOS compatible.
Data Strobe/Frame Pulse (Input).
For SSI mode this input determines the 8 bit timeslot
used by the device for both transmit and receive data. This active high signal has a repetition
rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS mode. CMOS level
compatible input.
15
D
in
16
STB/F0i
17
CLOCKin
Clock Input.
The clock provided to this input is used by the internal phone functions. In ST-
BUS mode this is the C4i input. In SSI synchronous mode, this is the Bit Clock input. In SSI-
asynchronous mode this is an asynchronous 4 MHz Master Clock input.
XSTL2
V
DD
Crystal Input (4.096 MHz).
Used in conjunction with the CLOCKin pin to provide the master
clock signal via external crystal.
Positive Power Supply (Input).
Nominally 5 volts.
18
19
20
21
22
23
24
25
26
27
28
HSPKR-
Inverting Handset Speaker (Output).
Output to the handset speaker (balanced).
HSPKR+
Non-Inverting Handset Speaker (Output).
Output to the handset speaker (balanced).
SPKR-
SPKR+
Inverting Speaker (Output).
Output to the speakerphone speaker (balanced).
Non-Inverting Speaker (Output).
Output to the speakerphone speaker (balanced).
V
SS
SPKR
Power Supply Rail for Speaker Driver.
Nominally 0 Volts.
AUX
out
AUX
in
MIC+
V
SSA
Auxiliary Port (Output).
Access point to the D/A (analog) signals of the receive path as well
as to the various analog inputs.
Auxiliary Port (Input).
An analog signal may be fed to the filter/codec transmit section and
various loopback paths via this pin. No external anti-aliasing is required.
Non-inverting on-hook answer back Microphone (Input).
Microphone amplifier non-
inverting input pin.
Analog Ground (Input).
Nominally 0 V.
Overview
The functional block diagram of Figure 1 depicts the main operations performed by the MT9196 IDPC. Each of
these functional blocks will be described individually in the sections to follow. This overview will describe some of
the end-user features which may be implemented as a direct result of the level of integration found within the IDPC.
The main feature required of a digital telephone is to convert the digital Pulse Code Modulated (PCM) information,
being received by the telephone set, into an analog electrical signal. This signal is then applied to an appropriate
audio transducer such that the information is finally converted into intelligible acoustic energy. The same is true of
the reverse direction where acoustic energy is converted first into an electrical analog and then digitized (into PCM)
before being transmitted from the set. Along the way if the signals can be manipulated, either in the analog or the
digital domains, other features such as gain control and signal generation may be added. Finally, most electro-
acoustic transducers (loudspeakers) require a large amount of power if they are to develop an acoustic signal. The
inclusion of audio amplifiers to provide this power is required.
3
Zarlink Semiconductor Inc.
MT9196
Data Sheet
The IDPC features complete Analog/Digital and Digital/Analog conversion of audio signals (Filter/CODEC) and an
analog interface to electro-acoustic devices (Transducer Interface). Full programmability of the receive path and
side-tone gains is available to set comfortable listening levels for the user. Transmit path gain control is available for
setting nominal transmit levels into the network. A digital, anti-feedback circuit permits both the handset microphone
and the speaker-phone speaker to be enabled at the same time for group listening applications. This anti-feedback
circuit limits the total loop gain there by preventing a singing condition from developing.
Signalling in digital telephone systems, behind the PBX or standard ISDN applications, is handled on the D-channel
and generally does not require DTMF tones. Locally generated tones, in the set, however, can be used to provided
“comfort tones” or “key confirmation” to the user, similar to the familiar DTMF tones generated by conventional
phones during initial call set-up. Also, as the network slowly evolves from the dial pulse/DTMF methods to the D-
Channel protocols it is essential that the older methods be available for backward compatibility. As an example,
once a call has been established (i.e., from your office to your home) using the D-Channel signalling protocol it may
be necessary to use in-band DTMF signalling to manipulate your personal answering machine in order to retrieve
messages. Thus the locally generated tones must be of network quality. The IDPC can generate the required tone
pairs as well as single tones to accommodate any in-band signalling requirement.
Each of the programmable parameters within the functional blocks is accessed through a serial microcontroller
port compatible with Intel MCS-51
®
, Motorola SPI
®
and National Semiconductor Microwire
®
specifications.
Functional Description
In this section each of the functional blocks within IDPC is described along with all of the associated control/status
bits. Each time a control/status bit(s) is described it is followed by the address register where it will be found. The
reader is referred to the section titled 'Register Summary' for a complete listing of all address registers, the
control/status bits associated with each register and a definition of the function of each control/status bit. The
Register Summary is useful for future reference of control/status bits without the need to locate them in the text of
the functional descriptions.
Filter/CODEC
The Filter/CODEC block implements conversion of the analog 3.3 kHz speech signals to/from the digital domain
compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are
register programmable. These are CCITT G.711 A-law or
µ-Law,
with true-sign/ Alternate Digit Inversion or true-
sign/Inverted Magnitude coding, respectively. Optionally, sign- magnitude coding may also be selected for
proprietary applications.
The Filter/CODEC block also implements transmit and receive audio path gains in the analog domain. These gains
are in addition to the digital gain pad section and provide an overall path gain resolution of 1.0 dB. A programmable
gain, voice side-tone path is also included to provide proportional transmit speech feedback to the handset receiver.
Figure 3 depicts the nominal half-channel and side-tone gains for the IDPC.
On PWRST (pin 5) the Filter/CODEC defaults such that the side-tone path, dial tone filter and 400 Hz transmit filter
are off, all programmable gains are set to 0 dB and CCITT
µ-Law
is selected. Further, the Filter/CODEC is powered
down due to the control bits of the Path Control Registers (addresses 12h and 13h) being reset.
The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide
dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the Transducer
Interface section to provide full chip realization of these capabilities for the handset and loudspeaker functions.
A reference voltage (V
Ref
), for the conversion requirements of the CODEC section, and a bias voltage (V
Bias
), for
biasing the internal analog sections, are both generated on-chip. V
Bias
is also brought to an external pin so that it
may be used for biasing external gain plan setting amplifiers. A 0.1
µF
capacitor must be connected from V
Bias
to
analog ground at all times. Likewise, although V
Ref
may only be used internally, a 0.1
µF
capacitor from the V
Ref
pin
to ground is required at all times. The analog ground reference point for these two capacitors must be physically the
same point. To facilitate this the V
Ref
and V
Bias
pins are situated on adjacent pins.
4
Zarlink Semiconductor Inc.
MT9196
Data Sheet
The transmit filter is designed to meet CCITT G.714 specifications. The nominal gain for this filter path is 0 dB (gain
control = 0 dB). Gain control allows the output signal to be increased up to 7 dB. An anti-aliasing filter is included.
This is a second order lowpass implementation with a corner frequency at 25 kHz. Attenuation is better than 32 dB
at 256 kHz and less than 0.01 dB within the passband.
An optional 400 Hz high-pass function may be included into the transmit path by enabling the Tfhp bit in the Control
Register 1 (address 0Eh). This option allows the reduction of transmitted background noise such as motor and fan
noise.
SERIAL
PORT
DIGITAL GAIN
& TONES
FILTER/CODEC
TRANSDUCER INTERFACE
-6.1 dB or
-3.6 dB
HSPKR +
Receive
Receiver
Driver
75
Handset
Receiver
(150Ω)
PCM
D
in
-24 to
+21 dB
(3dB steps)
Receive
Filter Gain
0 to -7 dB
(1 dB steps)
-6 dB
HSPKR -
75
Side-tone
-9.96 to
+9 96dB
(3.32 dB steps)
DTMF,
Tone
Ringer
-11 dB
Speaker
Phone
Driver
0 dB
SPKR +
SPKR -
0/+8dB
+8 to -20dB
(4 dB steps)
RINGER
0 to -28 dB
(4 dB steps)
Auxiliary
Out
Driver
-12 dB
AUXout
Speakerphone
Speaker
(40Ω nominal)
34Ω min)
PCM
D
out
-24 to
+21 dB
(3 dB steps)
Transmit
Transmit Filter
Gain
0 to +7 dB
(1 dB steps)
Trans-
mit
Gain
-0.37 dB
or 8.93 dB
Trans-
mit
Gain
6.37 dB
5 dB
M
U
X
5 dB
AUXin AUX input
MIC+
H/F answer-
back mic
M + Transmitter
microphone
M-
Digital Domain
Analog Domain
Internal To Device
External To Device
Figure 3 - Audio Gain Partitioning
The receive filter is designed to meet CCITT G.714 specifications. The nominal gain for this filter path is 0 dB (gain
control = 0dB). Gain control allows the output signal to be attenuated up to 7 dB. Filter response is peaked to
compensate for the sinx/x attenuation caused by the 8 kHz sampling rate.
The Rx filter function can be altered by enabling the Dial EN control bit in Control Register 1 (address 0Eh). This
causes another low-pass function to be added with a 3 dB point at 1200 Hz. This function is intended to improve the
sound quality of digitally generated dial tone received as PCM.
Side-tone is derived from the Tx filter before the LP/HP filter section and is not subject to the gain control of the Tx
filter section. Side-tone is summed into the receive handset transducer driver path after the Rx filter gain control
5
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