MT9043
T1/E1 System Synchronizer
Data Sheet
Features
•
Supports AT&T TR62411 and Bellcore GR-1244-
CORE, Stratum 4 Enhanced and Stratum 4 timing
for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or
8 kHz input reference signals
Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9 Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
Accepts reference inputs from two independent
sources
JTAG Boundary Scan
Ordering Information
MT9043AN
48 pin SSOP
MT9043ANR 48 Pin SSOP
MT9043AN1 48 Pin SSOP*
MT9043ANR1 48 Pin SSOP*
*Pb Free Matte Tin
Tubes
Tape & Reel
Tubes
Tape & Reel
September 2009
•
•
•
-40°C to +85°C
Description
The MT9043 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides timing
and synchronization signals for multitrunk T1 and E1
primary rate transmission links.
The MT9043 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048 MHz, 1.544 MHz, or 8 kHz input reference.
The MT9043 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE, Stratum 4 Enhanced, and
Stratum 4; and ETSI ETS 300 011. It will meet the
jitter/wander tolerance, jitter transfer, intrinsic jitter,
frequency accuracy, capture range, phase change
slope, and MTIE requirements for these specifications.
•
•
•
•
•
•
Applications
•
•
Synchronization and timing control for multitrunk
T1,E1 and STS-3/OC3 systems
ST-BUS clock and frame pulse sources
OSCi
OSCo
TCLR
LOCK
VDD
VSS
Master Clock
TCK
TDI
TMS
TRST
TDO
PRI
SEC
IEEE
1149.1a
TIE
Corrector
Circuit
Virtual
Reference
DPLL
Output
Interface
Circuit
Reference
Select
MUX
Selected
Reference
TIE
Corrector
Enable
State
Select
Input
Impairment
Monitor
Reference
Select
RSEL
Control State Machine
State
Select
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
Feedback
Frequency
Select
MUX
MS
RST
IM
FLOCK
FS1
FS2
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2009, Zarlink Semiconductor Inc. All Rights Reserved.
MT9043
Change Summary
Below are the changes from the February 2005 issue.
Data Sheet
Page
2
Pin Description
Item
Description
Corrected pin name from RST to RSP.
V
SS
RST
TCLR
IC
SEC
PRI
Vdd
OSCo
OSCi
Vss
F16o
F0o
RSP
TSP
F8o
C1.5o
Vdd
LOCK
C2o
C4o
C19o
FLOCK
Vss
IC
1
48
2
47
3
46
45
4
5
44
6
43
42
7
8
41
40
9
10
MT9043AN
39
38
11
37
12
36
13
14
35
34
15
16
33
32
17
31
18
30
19
29
20
21
28
22
27
26
23
24
25
TMS
TCK
TRST
TDI
TDO
IC
IC
FS1
FS2
IC
RSEL
IC
MS
Vdd
IC
IC
NC
Vss
IC
IM
Vdd
C6o
C16o
C8o
Figure 2 - Pin Connections
Pin Description
Pin #
1,10,
23,31
2
Name
V
SS
RST
Ground.
0 Volts. (Vss pads).
Reset (Input).
A logic low at this input resets the MT9043. To ensure proper operation, the
device must be reset after reference signal frequency changes and power-up. The RST
pin should be held low for a minimum of 300 ns. While the RST pin is low, all frame pulses
except RSP and TSP and all clock outputs except C6o, C16o and C19o are at logic high.
The RSP, TSP, C6o and C16o are at logic low during reset. The C19o is free-running
during reset. Following a reset, the input reference source and output clocks and frame
pulses are phase aligned as shown in Figure 12.
TIE Circuit Reset (Input).
A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase as shown in
Figure 13. The TCLR pin should be held low for a minimum of 300 ns. This pin is internally
pulled down to VSS.
Internal Connection.
Leave open circuit.
Description
3
TCLR
4
IC
2
Zarlink Semiconductor Inc.
MT9043
Pin Description
Pin #
5
Name
SEC
Description
Data Sheet
Secondary Reference (Input).
This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of four possible frequencies (8 kHz, 1.544 MHz,
2.048 MHz or 19.44 MHz) may be used. The selection of the input reference is based upon
the MS, and RSEL, control inputs.This pin is internally pulled up to V
DD
.
Primary Reference (Input).
See pin description for SEC. This pin is internally pulled up to
V
DD
.
Positive Supply Voltage.
+3.3V
DC
nominal.
Oscillator Master Clock (CMOS Output).
For crystal operation, a 20 MHz crystal is
connected from this pin to OSCi, see Figure 9. Not suitable for driving other devices. For
clock oscillator operation, this pin is left unconnected, see Figure 8.
Oscillator Master Clock (CMOS Input).
For crystal operation, a 20 MHz crystal is
connected from this pin to OSCo, see Figure 9. For clock oscillator operation, this pin is
connected to a clock source, see Figure 8.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output).
This is an 8 kHz 61 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 8.192 Mb/s. See Figure 14.
Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output).
This is an 8 kHz 244 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 2.048 Mb/s and 4.096 Mb/s. See Figure 14.
Receive Sync Pulse (CMOS Output).
This is an 8 kHz 488 ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
Transmit Sync Pulse (CMOS Output).
This is an 8 kHz 488 ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
Frame Pulse (CMOS Output).
This is an 8 kHz 122 ns active high framing pulse, which
marks the beginning of a frame. See Figure 14.
Clock 1.544 MHz (CMOS Output).
This output is used in T1 applications.
Lock Indicator (CMOS Output).
This output goes high when the PLL is frequency locked to
the input reference.
Clock 2.048 MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048 Mb/s.
Clock 4.096 MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048 Mb/s
and 4.096 Mb/s.
Clock 19.44 MHz (CMOS Output).
This output is used in OC3/STS3 applications.
Fast Lock Mode (Input).
Set high to allow the PLL to quickly lock to the input reference (less
than 500 ms locking time).
Internal Connection.
Tie low for normal operation.
Clock 8.192 MHz (CMOS Output).
This output is used for ST-BUS operation at 8.192 Mb/s.
Clock 16.384 MHz (CMOS Output).
This output is used for ST-BUS operation with a
16.384 MHz clock.
6
7,17
28,35
8
PRI
V
DD
OSCo
9
OSCi
11
F16o
12
F0o
13
RSP
14
TSP
15
16
18
19
20
21
22
24
25
26
F8o
C1.5o
LOCK
C2o
C4o
C19o
FLOCK
IC
C8o
C16o
3
Zarlink Semiconductor Inc.
MT9043
Pin Description
Pin #
27
29
30
32
33,34
36
37
38
Name
C6o
IM
IC
NC
IC
MS
IC
RSEL
Description
Clock 6.312 Mhz (CMOS Output).
This output is used for DS2 applications.
Data Sheet
Impairment Monitor (CMOS Output).
A logic high on this pin indicates that the Input
Impairment Monitor has automatically put the device into Freerun Mode.
Internal Connection.
Tie high for normal operation.
No Connection.
Leave open circuit.
Internal Connection.
Tie low for normal operation.
Mode/Control Select (Input).
This input determines the state (Normal or Freerun) of
operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3.
Internal Connection.
Tie low for normal operation.
Reference Source Select (Input).
A logic low selects the PRI (primary) reference source as
the input reference signal and a logic high selects the SEC (secondary) input. The logic level
at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled
down to VSS.
Internal Connection.
Tie low for normal operation.
Frequency Select 2 (Input).
This input, in conjunction with FS1, selects which of four
possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI
and SEC inputs. See Table 1.
Frequency Select 1 (Input).
See pin description for FS2.
Internal Connection.
Tie Low for Normal Operation.
Internal Connection.
Leave Open Circuit.
Test Serial Data Out (CMOS Output).
JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
Test Serial Data In (Input).
JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
DD
.
Test Reset (Input).
Asynchronously initializes the JTAG TAP controller by putting it in the
Test-Logic-Reset state. If not used, this pin should be held low.
Test Clock (Input).
Provides the clock to the JTAG test logic. This pin is internally pulled up
to V
DD
.
Test Mode Select (Input).
JTAG signal that controls the state transitions of the TAP
controller. This pin is internally pulled up to V
DD
.
39
40
IC
FS2
41
42
43
44
45
46
47
48
FS1
IC
IC
TDO
TDI
TRST
TCK
TMS
4
Zarlink Semiconductor Inc.
MT9043
Functional Description
Data Sheet
The MT9043 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which
is described in the following sections.
Reference Select MUX Circuit
The MT9043 accepts two simultaneous reference input signals and operates on their falling edges. Either the
primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE
Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1
and Table 4.
Frequency Select MUX Circuit
The MT9043 operates with one of four possible input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used at
the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST)
must be performed after every frequency select input change. See Table 1.
FS2
0
0
1
1
FS1
0
1
0
1
Input Frequency
19.44 MHz
8 kHz
1.544 MHz
2.048 MHz
Table 1 - Input Frequency Selection
5
Zarlink Semiconductor Inc.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
