MT8980D
ISO-CMOS ST-BUS
TM
Family
Digital Switch
Data Sheet
Features
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•
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Zarlink ST-BUS compatible
8-line x 32-channel inputs
8-line x 32-channel outputs
256 ports non-blocking switch
Single power supply (+5 V)
Low power consumption: 30 mW Typ.
Microprocessor-control interface
Three-state serial outputs
MT8980DP1
MT8980DE1
MT8980DPR1
44 Pin PLCC*
40 Pin PDIP*
44 Pin PLCC*
Tubes
Tubes
Tape & Reel
Ordering Information
April 2011
*Pb Free Matte Tin
-40°C to +85°C
Description
This VLSI ISO-CMOS device is designed for switching
PCM-encoded voice or data, under microprocessor
control, in a modern digital exchange, PBX or Central
Office. It provides simultaneous connections for up to
256 64 kbit/s channels. Each of the eight serial inputs
and outputs consist of 32 64 kbit/s channels
multiplexed to form a 2048 kbit/s ST-BUS stream. In
addition, the MT8980 provides microprocessor read
and write access to individual ST-BUS channels.
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.
MT8980D
Change Summary
Changes from February 2005 Issue to April 2011 Issue.
Page
1
Item
Ordering Information
Change
Data Sheet
Obsolete Leaded packages, only Pb Free packages are
available.
Figure 2 - Pin Connections
Pin Descripton
Pin #
40
DIP
1
44
PLCC
2
Name
DTA
Description
Data Acknowledgement (Open Drain Output).
This is the data
acknowledgement on the microprocessor interface. This pin is pulled low to signal
that the chip has processed the data. A 909
1/4W, resistor is recommended to be
used as a pullup.
ST-BUS Input 0 to 2 (Inputs).
These are the inputs for the 2048 kbit/s ST-BUS
input streams.
ST-BUS Input 3 to 7 (Inputs).
These are the inputs for the 2048 kbit/s ST-BUS
input streams.
Power Input.
Positive Supply.
Framing 0-Type (Input).
This is the input for the frame synchronization pulse for
the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to
reset on the next negative transition of C4i.
2-4
5-9
10
11
3-5
7-11
12
13
STi0-
STi2
STi3-
STi7
V
DD
F0i
2
Zarlink Semiconductor Inc.
MT8980D
Pin Descripton
Pin #
40
DIP
12
13-15
16-18
19
20
21
22-24
25-29
30
31-35
36-38
39
44
PLCC
14
15-17
19-21
22
23
24
25-27
29-33
34
35-39
41-43
44
Name
C4i
A0-A2
A3-A5
DS
R/W
CS
D7-D5
D4-D0
V
SS
STo7-
STo3
STo2-
STo0
ODE
Description
Data Sheet
4.096 MHz Clock (Input).
ST-BUS bit cell boundaries lie on the alternate falling
edges of this clock.
Address 0 to 2 (Inputs).
These are the inputs for the address lines on the
microprocessor interface.
Address 3 to 5 (Inputs).
These are the inputs for the address lines on the
microprocessor interface.
Data Strobe (Input).
This is the input for the active high data strobe on the
microprocessor interface.
Read or Write (Input).
This is the input for the read/write signal on the
microprocessor interface - high for read, low for write.
Chip Select (Input).
This is the input for the active low chip select on the
microprocessor interface.
Data 7 to 5 (Three-state I/O Pins).
These are the bidirectional data pins on the
microprocessor interface.
Data 4 to 0 (Three-state I/O Pins).
These are the bidirectional data pins on the
microprocessor interface.
Power Input.
Negative Supply (Ground).
ST-BUS Output 7 to 3 (Three-state Outputs).
These are the pins for the eight
2048 kbit/s ST-BUS output streams.
ST-BUS Output 2 to 0 (Three-state Outputs).
These are the pins for the eight
2048 kbit/s ST-BUS output streams.
Output Drive Enable (Input).
If this input is held high, the STo0-STo7 output
drivers function normally. If this input is low, the STo0-STo7 output drivers go into
their high impedance state.
NB:
Even when ODE is high, channels on the STo0-
STo7 outputs can go high impedance under software control.
Control ST-BUS Output (Complementary Output).
Each frame of 256 bits on
this ST-BUS output contains the values of bit 1 in the 256 locations of the
Connection Memory High.
No Connection.
40
1
CSTo
6, 18,
28, 40
NC
Functional Description
In recent years, there has been a trend in telephony towards digital switching, particularly in association with
software control. Simultaneously, there has been a trend in system architectures towards distributed processing or
multi-processor systems.
In accordance with these trends, Zarlink has devised the ST-BUS (Serial Telecom Bus). This bus architecture can
be used both in software-controlled digital voice and data switching, and for interprocessor communications. The
uses in switching and in interprocessor communications are completely integrated to allow for a simple general
purpose architecture appropriate for the systems of the future.
3
Zarlink Semiconductor Inc.
MT8980D
Data Sheet
The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 µs wide frames
which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST-BUS; a key
device being the MT8980 chip.
The MT8980 can switch data from channels on ST-BUS inputs to channels on ST-BUS outputs, and simultaneously
allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST-BUS outputs
(Message Mode). To the microprocessor, the MT8980 looks like a memory peripheral. The microprocessor can
write to the MT8980 to establish switched connections between input ST-BUS channels and output ST-BUS
channels, or to transmit messages on output ST-BUS channels. By reading from the MT8980, the microprocessor
can receive messages from ST-BUS input channels or check which switched connections have already been
established.
By integrating both switching and interprocessor communications, the MT8980 allows systems to use distributed
processing and to switch voice or data in an ST-BUS architecture.
Hardware Description
Serial data at 2048 kbit/s is received at the eight ST-BUS inputs (STi0 to STi7), and serial data is transmitted at the
eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel
containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g.,
Zarlink’s MT8964).
This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory. Locations in the Data
Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read
by the microprocessor which controls the chip.
Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS
output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either
be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input,
then the contents of the Connection Memory Low location associated with the output channel is used to address
the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the
data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode),
then the contents of the Connection Memory Low location associated with the output channel are output directly,
and this data is output repetitively on the channel once every frame until the microprocessor intervenes.
The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives
address information at A5 to A0 and handles the microprocessor control signals CS, DTA, R/W and DS. There are
two parts to any address in the Data Memory or Connection Memory. The higher order bits come from the Control
Register, which may be written to or read from via the Control Interface. The lower order bits come from the address
lines directly.
The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel
into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the
Connection Memory Low. The Connection Memory High determines whether individual output channels are in
Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of
MT8980s to be constructed. It also controls the CSTo pin.
All ST-BUS timing is derived from the two signals C4i and F0i.
4
Zarlink Semiconductor Inc.
MT8980D
Data Sheet
Figure 3 - Address Memory Map
Software Control
The address lines on the Control Interface give access to the Control Register directly or, depending on the
contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.
If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If
A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory
and stream selected in the Control Register.
The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see
Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and
the stream address bits define one of the ST-BUS input or output streams.
5
Zarlink Semiconductor Inc.
传感器
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