ISO
2
-CMOS ST-BUS
TM
Family
MT9173/74
Digital Subscriber Interface Circuit with RxSB
Digital Network Interface Circuit with RxSB
Data Sheet
March 2013
Features
•
•
•
•
•
•
•
•
•
•
Receive sync output pulse
Full duplex transmission over a single twisted pair
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
Up to 3 km (9173) and 4 km (9174) loop reach
Integrated services digital network (ISDN)
compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
Microsemi
®
ST-BUS compatible
Low power (typically 50 mW), single 5 V supply
Ordering Information
MT9173AE1
MT9173AP1
MT9173AN1
MT9173ANR1
MT9174AN1
MT9174AP1
24 Pin PDIP*
28 Pin PLCC*
24 Pin SSOP*
24 Pin SSOP*
24 Pin SSOP*
28 Pin PLCC*
*Pb Free Matte Tin
Tubes
Tubes
Tubes
Tape & Reel
Tubes
Tubes
-40C to +85C
Description
The MT9173 (DSIC) and MT9174 (DNIC) are
functionally identical to the MT9171/72 except for the
addition of one feature. The MT9173/74 include a
digital output pin indicating the temporal position of the
received "SYNC" bit of the biphase transmission. This
feature is especially useful for systems such as PCS
wireless base station applications requiring close
synchronization between microcells.
The MT9173 and MT9174 are identical except for the
MT9173 having a shorter loop reach. The generic
"DNIC" is used to refer both the devices unless
otherwise noted. The MT9173/74 are fabricated in
Microsemi ISO
2
-CMOS process.
Applications
•
•
•
•
•
T
DD
Digital PCS (DECT, CT2, PHS) base stations
requiring cell synchronization
Digital subscriber lines
High speed data transmission over twisted wires
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
DSTi/Di
CDSTi/
CDi
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
L
OUT
F0/CLD
C4/TCK
MS0
MS1
MS2
RegC
Control
Register
Transmit
Timing
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control
Sync Detect
Status
Receive
Address
Echo Canceller
Error
Signal
Echo Estimate
—
DPLL
V
Bias
MUX
L
OUT
DIS
Precan
+
Receive
Filter
-1
+2
L
IN
OSC2
DSTo/Do
CDSTo/
CDo
RxSB
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
OSC1
V
DD
V
SS
V
Bias
V
Ref
Figure 1 - Functional Block Diagram
1
Copyright 2013, Microsemi Corporation. All Rights Reserved.
MT9173/74
Change Summary
Data Sheet
Below are the changes made in March 2013 issue. Page, section, figure, and table numbers refer to this current
issue.
Page
Multiple
1
Item
Zarlink logo and name reference
“Ordering Information“
Change
Updated to Microsemi logo and name.
Removed the following packages:
• MT9173AE 24 Pin PDIP Tubes
• MT9173AN 24 Pin SSOP Tubes
• MT9173AP 28 Pin PLCC Tubes
Changed MT9173AN1 from 'Tape & Reel' to 'Tubes'.
Added new MT9173ANR1 package.
Added Pb-free marking to MT9174 packages (for example,
'1' and '*')
21
21
Figure 17
“AC Electrical Characteristics† -
Clock Timing - MOD Mode (Figure
18)“
Changed symbol from 'F' to ''.
Changed unit to 'ns' for item 3.
2
Microsemi Corporation
MT9173/74
Data Sheet
24 PIN PDIP/ SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
24
1
2
3
4,5,
6
7
8
28
2
3
4
5,7,
8
9
10
L
OUT
V
Bias
V
Ref
Line Out.
Transmit Signal output (Analog). Referenced to V
Bias
.
Internal Bias Voltage
output. Connect via 0.33
F
decoupling capacitor to V
DD
.
Internal Reference Voltage
output. Connect via 0.33
F
decoupling capacitor to V
DD
.
Description
MS2-MS0
Mode Select
inputs (Digital). The logic levels present on these pins select the various
operating modes for a particular application. See Table 1 for the operating modes.
RegC
RxSB
Regulator Control
output (Digital). A 512 kHz clock used for switch mode power
supplies. Unused in MAS/MOD mode and should be left open circuit.
Receive Sync Bit
output (Digital). In DN mode, this output is held high until receive
synchronization occurs (i.e., until the sync bit in Status Register =1). Once low,
indicating synchronized transmission, a high going pulse (6.24
s
wide pulse @
160 kb/s and 12.5
s
wide @ 80 kb/s) indicates the temporal position of the receive
"SYNC" bit in the biphase line transmission. Inactive and low in MOD mode.
Frame Pulse/C-Channel Load
(Digital). In DN mode a 244 ns wide negative pulse
input for the MASTER indicating the start of the active channel times of the device.
Output for the SLAVE indicating the start of the active channel times of the device.
Output in MOD mode providing a pulse indicating the start of the C-channel.
Control/Data ST-BUS In/Control/Data In
(Digital). A 2.048 Mbit/s serial control &
signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit
rate selected.
Control/Data ST-BUS Out/Control/Data Out
(Digital). A 2.048 Mbit/s serial control &
signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit
rate selected.
Negative Power Supply
(0 V).
9
11
F0/CLD
10
12
CDSTi/
CDi
CDSTo/
CDo
V
SS
11
13
12
14
3
Microsemi Corporation
CDSTi/CDi
CDSTo/CDo
VSS
DSTo/Do
DSTi/Di
F0o/RCK
NC
LOUT
VBias
VRef
MS2
MS1
MS0
RegC
RxSB
F0/CLD
CDSTi/CDi
CDSTo/CDo
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
NC
OSC2
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do
4
3
2
1
28
27
26
²
VRef
VBias
LOUT
NC
VDD
LIN
TEST
12
13
14
15
16
17
18
MS2
NC
MS1
MS0
RegC
RxSB
F0/CLD
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC
LOUT DIS
Precan
OSC1
OSC2
NC
C4/TCK
28 PIN PLCC
MT9173/74
Pin Description (continued)
Pin #
Name
24
13
14
15
28
15
16
17
DSTo/Do
DSTi/Di
Description
Data Sheet
Data ST-BUS Out/Data Out
(Digital). A 2.048 Mbit/s serial PCM/data output in DN
mode. In MOD mode this is a continuous bit stream at the bit rate selected.
Data ST-BUS In/Data In
(Digital). A 2.048 Mbit/s serial PCM/data input in DN mode.
In MOD mode this is a continuous bit stream at the bit rate selected.
F0o/RCK
Frame Pulse Out/Receive Bit Rate Clock
output (Digital). In DN mode a 244 ns wide
negative pulse indicating the end of the active channel times of the device to allow
daisy chaining. In MOD mode provides the receive bit rate clock to the system.
C4/TCK
Data Clock/Transmit Baud Rate Clock
(Digital). A 4.096 MHz TTL compatible clock
input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin
provides the transmit bit rate clock to the system.
Oscillator Output.
CMOS Output.
Oscillator Input.
CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical
Characteristics for OSC1 input requirements.
Precanceller Disable.
When held to Logic ’1’
,
the internal path from L
OUT
to the
precanceller is forced to V
Bias
thus bypassing the precanceller section. When logic ’0’,
the L
OUT
to the precanceller path is enabled and functions normally. An internal
pulldown (50 k) is provided on this pin.
No Connection.
Leave open circuit
16
19
17
19
20
21
22
23
OSC2
OSC1
Precan
18
1,6,
18,
20,
25
24
26
27
28
NC
21
22
23
24
L
OUT
DIS
L
OUT
Disable.
When held to logic “1”, L
OUT
is disabled (i.e., output = V
Bias
). When logic
“0”, L
OUT
functions normally. An internal pull-down (50 k) is provided on this pin.
TEST
L
IN
V
DD
Test Pin.
Connect to V
SS
.
Receive Signal
input (Analog).
Positive Power Supply
(+5 V) input.
4
Microsemi Corporation
MT9173/74
Data Sheet
F0
C4
DSTi
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B1
7
DSTo
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B1
7
F0o
Channel Time 0
Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)
F0
C4
DSTi
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B2
7
B2
6
B2
5
B2
4
B2
3
B2
2
B2
1
B2
0
B1
7
DSTo
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B2
7
B2
6
B2
5
B2
4
B2
3
B2
2
B2
1
B2
0
B1
7
F0o
Channel Time 0
Channel Time 16
Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6)
5
Microsemi Corporation
NXP MCU
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