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MT48H32M16LFBF-6:B

产品描述IC sdram 512mbit 166mhz 54vfbga
产品类别存储   
文件大小2MB,共86页
制造商Micron(美光)
官网地址http://www.micron.com/
标准  
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MT48H32M16LFBF-6:B概述

IC sdram 512mbit 166mhz 54vfbga

MT48H32M16LFBF-6:B规格参数

参数名称属性值
Datasheets
MT48H32M16LF, 16M32(LF,LG) B
PCN Obsolescence/ EOL
MT48H Family 13/Apr/2010
Standard Package1,000
CategoryIntegrated Circuits (ICs)
FamilyMemory
系列
Packaging
Tray
Format - MemoryRAM
Memory TypeMobile LPSDR SDRAM
Memory Size512M (32M x 16)
速度
Speed
166MHz
InterfaceParallel
Voltage - Supply1.7 V ~ 1.95 V
Operating Temperature0°C ~ 70°C
封装 / 箱体
Package / Case
54-VFBGA
Supplier Device Package54-VFBGA (6x9)

文档预览

下载PDF文档
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Features
Mobile Low-Power SDR SDRAM
MT48H32M16LF – 8 Meg x 16 x 4 banks
MT48H16M32LF/LG – 4 Meg x 32 x 4 banks
Features
V
DD
/V
DDQ
= 1.7–1.95V
Fully synchronous; all signals registered on positive
edge of system clock
Internal, pipelined operation; column address can
be changed every clock cycle
Four internal banks for concurrent operation
Programmable burst lengths: 1, 2, 4, 8, and continu-
ous
Auto precharge, includes concurrent auto precharge
Auto refresh and self refresh modes
LVTTL-compatible inputs and outputs
On-chip temperature sensor to control self refresh
rate
Partial-array self refresh (PASR)
Deep power-down (DPD)
Selectable output drive strength (DS)
64ms refresh period
V
DD
/V
DDQ
: 1.8V/1.8V
Addressing
Standard addressing option
Reduced page-size option
1
Configuration
32 Meg x 16 (8 Meg x 16 x 4 banks)
16 Meg x 32 (4 Meg x 32 x 4 banks)
Plastic “green” packages
54-ball VFBGA (8mm x 9mm)
2
90-ball VFBGA (10mm x 13mm)
3
Timing – cycle time
6ns at CL = 3
7.5ns at CL = 3
Power
Standard I
DD2
/I
DD7
Low-power I
DD2
/I
DD71
Operating temperature range
Commercial (0˚C to +70˚C)
Industrial (–40˚C to +85˚C)
Revision
Notes:
Options
Marking
H
LF
LG
32M16
16M32
BF
CM
-6
-75
None
L
None
IT
:B
1. Contact factory for availability.
2. Available only for x16 configuration.
3. Available only for x32 configuration.
Table 1: Configuration Addressing
Architecture
Number of banks
Bank address balls
Row address balls
Column address balls
Note: 1. Contact factory for availability
32 Meg x 16
4
BA0, BA1
A[12:0]
A[9:0]
16 Meg x 32
4
BA0, BA1
A[12:0]
A[8:0]
16 Meg x 32 Reduced
Page-Size Option
1
4
BA0, BA1
A[13:0]
A[7:0]
Table 2: Key Timing Parameters
Clock Rate (MHz)
Speed Grade
-6
Note:
CL = 2
104
CL = 3
166
133
CL = 2
8ns
8ns
Access Time
CL = 3
5ns
5.4ns
-75
104
1. CL = CAS (READ) latency
PDF: 09005aef82ea3742
512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2007 Micron Technology, Inc. All rights reserved.

 
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