MT8889C
Integrated DTMF Transceiver
with Adaptive Micro Interface
Data Sheet
Features
•
•
•
•
•
•
Central office quality DTMF transmitter/receiver
Low power consumption
High speed adaptive micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30 dBm
Ordering Information
MT8889CE
MT8889CS
MT8889CN
MT8889CE1
MT8889CS1
MT8889CN1
MT8889CPR
MT8889CSR
MT8889CSR1
*Pb
20 Pin PDIP
20 Pin SOIC
24 Pin SSOP
20 Pin PDIP*
20 Pin SOIC*
24 Pin SSOP*
28 Pin PLCC
20 Pin SOIC
20 Pin SOIC*
Free Matte Tin
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tape & Reel
September 2005
Applications
•
•
•
•
•
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
-40°C to +85°C
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT8889C utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external logic.
Description
The MT8889C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
TONE
∑
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
DS/RD
CS
R/W/WR
RS0
Steering
Logic
Receive Data
Register
V
DD
V
Ref
V
SS
ESt
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT8889C
Functional Description
Data Sheet
The MT8889C Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain
setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and
pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.
The adaptive micro interface allows microcontrollers, such as the 68HC11, 80C51 and TMS370C50, to access the
MT8889C internal registers.
20 PIN PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
20
1
2
3
4
5
6
7
24
1
2
3
4
5
6
7
28
1
2
4
6
7
8
9
Name
IN+
IN-
GS
V
Ref
V
SS
OSC1
OSC2
Non-inverting
op-amp input.
Inverting
op-amp input.
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage
output (V
DD
/2).
Ground (0V).
DTMF clock/oscillator input. Connect a 4.7 M
Ω
resistor to VSS if crystal oscillator is
used.
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
Output from internal DTMF transmitter.
Description
8
9
10
11
12
10
11
12
13
14
12
13
14
15
17
TONE
R/W (WR) (Motorola)
Read/Write
or (Intel)
Write
microprocessor input. TTL compatible.
CS
RS0
Chip Select
input. This signal must be qualified externally by either address strobe (AS),
valid memory address (VMA) or address latch enable (ALE) signal, see Figure 14.
Register Select
input. Refer to Table 3 for bit interpretation. TTL compatible.
DS (RD) (Motorola)
Data Strobe
or (Intel)
Read
microprocessor input. Activity on this input is
only required when the device is being accessed. TTL compatible.
2
Zarlink Semiconductor Inc.
TONE
R/W/WR
CS
RSO
NC
DS/RD
IRQ/CP
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
12
13
14
15
16
17
18
NC
VRef
VSS
OSC1
OSC2
NC
NC
4
3
2
1
28
27
26
GS
NC
IN-
IN+
VDD
St/GT
EST
5
6
7
8
9
10
11
•
25
24
23
22
21
20
19
NC
NC
NC
D3
D2
D1
D0
28 PIN PLCC
MT8889C
Pin Description (continued)
Pin #
20
13
24
15
28
18
Name
Description
Data Sheet
IRQ/CP
Interrupt Request/Call Progress
(open drain) output. In interrupt mode, this output
goes low when a valid DTMF tone burst has been transmitted or received. In call progress
mode, this pin will output a rectangular signal representative of the input signal applied at
the input op-amp. The input signal must be within the bandwidth limits of the call
progress filter, see Figure 8.
D0-D3
ESt
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). TTL compatible.
Early Steering
output. Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt
to return to a logic low.
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
TSt
detected
at St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
TSt
frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on
St.
Positive power supply (5 V typical).
No Connection.
14-17 18-21 19-22
18
22
26
19
23
27
St/GT
20
24
28
V
DD
NC
8, 9, 3,5,10,
16,17 11,16,
23-25
1.0
Input Configuration
The input arrangement of the MT8889C provides a differential-input operational amplifier as well as a bias source
(V
Ref
), which is used to bias the inputs at V
DD
/2. Provision is made for connection of a feedback resistor to the op-
amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in
Figure 3.
Figure 4 shows the necessary connections for a differential input configuration.
2.0
Receiver Section
Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order
switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies
(see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each
filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the
incoming DTMF signals.
3
Zarlink Semiconductor Inc.
MT8889C
IN+
Data Sheet
C
R
IN
IN-
R
F
GS
V
Ref
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
MT8889C
Figure 3 - Single-Ended Input Configuration
C1
R1
IN+
IN-
C2
R4
R5
GS
R3
R2
V
Ref
MT8889C
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(A
V
diff) - R5/R1
INPUT IMPEDANCE
(Z
IN
diff) = 2 R1
2
+ (1/ωC)
2
Figure 4 - Differential Input Configuration
F
LOW
697
697
697
770
770
770
F
HIGH
1209
1336
1477
1209
1336
1477
DIGIT
1
2
3
4
5
6
D
3
0
0
0
0
0
0
D
2
0
0
0
1
1
1
D
1
0
1
1
0
0
1
D
0
1
0
1
0
1
0
Table 1 - Functional Encode/Decode Table
4
Zarlink Semiconductor Inc.
MT8889C
F
LOW
852
852
852
941
941
941
697
770
852
941
0= LOGIC LOW, 1= LOGIC HIGH
Data Sheet
D
2
1
0
0
0
0
1
1
1
1
0
F
HIGH
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
DIGIT
7
8
9
0
*
#
A
B
C
D
D
3
0
1
1
1
1
1
1
1
1
0
D
1
1
0
0
1
1
0
0
1
1
0
D
0
1
0
1
0
1
0
1
0
1
0
Table 1 - Functional Encode/Decode Table (continued)
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state.
3.0
Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes v
c
(see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt
remains high) for the validation period (t
GTP
), v
c
reaches the threshold (V
TSt
) of the steering logic to register the
tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT
output is activated and drives v
c
to V
DD
. GT continues to drive high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received
tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate
bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed
steering flag is active.
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the
four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to
validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together
with the capability of selecting the steering time constants externally, allows the designer to tailor performance to
meet a wide variety of system requirements.
5
Zarlink Semiconductor Inc.
FPGA/CPLD
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