MT8880C
Integrated DTMF Transceiver
Data Sheet
Features
•
•
•
•
•
•
•
Complete DTMF transmitter/receiver
Central office quality
Low power consumption
Microprocessor port
Adjustable guard time
Automatic tone burst mode
Call progress mode
Ordering Information
MT8880CE
MT8880CS
MT8880CN
MT8880CP
MT8880CP1
MT8880CS1
MT8880CE1
MT8880CN1
MT8880CSR
MT8880CPR
MT8880CPR1
MT8880CSR1
20 Pin PDIP
20 Pin SOIC
24 Pin SSOP
28 Pin PLCC
28 Pin PLCC*
20 Pin SOIC*
20 Pin PDIP*
24 Pin SSOP*
20 Pin SOIC
28 Pin PLCC
28 Pin PLCC*
20 Pin SOIC*
*Pb Free Matte Tin
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape &
Tape &
Tape &
Tape &
September 2005
ISO
2
- CMOS
Reel
Reel
Reel
Reel
Applications
•
•
•
•
•
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
-40°C to +85°C
Description
The MT8880C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in Zarlink
Semiconductor’s ISO
2
-CMOS technology, which
provides low power dissipation and high reliability. The
DTMF receiver is based upon the industry standard
MT8870 monolithic DTMF receiver; the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze
call
progress
tones.
A
standard
microprocessor bus is provided and is directly
compatible with 6800 series microprocessors.
TONE
∑
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
Φ2
CS
R/W
RS0
Steering
Logic
Receive Data
Register
V
DD
V
Ref
V
SS
ESt
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT8880C
Data Sheet
20 PIN PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
20
1
2
3
4
5
6
7
8
9
10
11
12
13
24
1
2
3
4
5
6
7
10
11
12
13
14
15
28
1
2
4
6
7
8
9
12
13
14
15
17
18
Name
IN+ Non-inverting op-amp input.
IN-
GS
Inverting op-amp input.
Gain Select.
Gives access to output of front end differential amplifier for connection of feedback
resistor.
Description
V
Ref
Reference Voltage
output, nominally V
DD
/2 is used to bias inputs at mid-rail (see Fig. 13).
V
SS
Ground input (0 V).
OSC1 DTMF clock/oscillator input. Connect a 4.7 M
Ω
resistor to VSS if crystal oscillator is used.
OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
TONE
Tone
output (DTMF or single tone).
R/W
Read/Write
input. Controls the direction of data transfer to and from the MPU and the transceiver
registers. TTL compatible.
CS
Chip Select,
TTL input (CS=0 to select the chip).
RS0
Register Select
input. See register decode table. TTL compatible.
Φ2
System Clock
input. TTL compatible.
N.B.
Φ2
clock input need not be active when the device
is not being accessed.
IRQ/C
Interrupt Request to MPU
(open drain output). Also, when call progress (CP) mode has been
P selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal representative
of the input signal applied at the input op-amp. The input signal must be within the bandwidth
limits of the call progress filter. See Figure 8.
14- 18-21 19-22 D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or
Φ2
is low.
17
2
Zarlink Semiconductor Inc.
TONE
R/W
CS
RS0
NC
Φ2
IRQ/CP
12
13
14
15
16
17
18
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
Φ2
RS0
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W
CS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
Φ2
RS0
4
3
2
1
28
27
26
GS
NC
IN-
IN+
VDD
St/GT
EST
NC
VRef
VSS
OSC1
OSC2
NC
NC
5
6
7
8
9
10
11
•
25
24
23
22
21
20
19
NC
NC
NC
D3
D2
D1
D0
28 PIN PLCC
MT8880C
Pin Description
Pin #
20
18
24
22
28
26
Name
ESt
Description
Data Sheet
Early Steering
output. Presents a logic high once the digital algorithm has detected a valid tone
pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic
low.
19
23
27
St/GT
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
TSt
detected at St
causes the device to register the detected tone pair and update the output latch. A voltage less than
V
TSt
frees the device to accept a new tone pair. The GT output acts to reset the external steering
time-constant; its state is a function of ESt and the voltage on St.
V
DD
Positive power supply input (+5 V typical).
NC
No Connection.
20
24
28
8, 9, 3,5,10,1
16,17 1, 16,
23-25
Functional Description
The MT8880C Integrated DTMF Transceiver architecture consists of a high performance DTMF receiver with
internal gain setting amplifier and a DTMF generator which employs a burst counter such that precise tone bursts
and pauses can be synthesized. A call progress mode can be selected such that frequencies within the specified
passband can be detected. A standard microprocessor interface allows access to an internal status register, two
control registers and two data registers.
Input Configuration
The input arrangement of the MT8880C provides a differential-input operational amplifier as well as a bias source
(V
Ref
) which is used to bias the inputs at V
DD
/2. Provision is made for connection of a feedback resistor to the op-
amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in
Figure 3.
Figure 4 shows the necessary connections for a differential input configuration.
IN+
C
R
IN
IN-
R
F
GS
V
Ref
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
MT8880C
Figure 3 - Single-Ended Input Configuration
3
Zarlink Semiconductor Inc.
MT8880C
Receiver Section
Data Sheet
Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order
switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies
(see Fig. 7). These filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each
filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent detection of unwanted
low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF
signals.
C1
R1
IN+
IN-
C2
R4
R5
GS
R3
R2
V
Ref
MT8880C
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(A
V
diff) = R5/R1
INPUT IMPEDANCE
(Z
IN
diff) = 2 R1
2
+ (1/ωC)
2
Figure 4 - Differential Input Configuration
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state.
Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes v
c
(see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt
remains high) for the validation period (t
GTP
), v
c
reaches the threshold (V
TSt
) of the steering logic to register the
tone pair, latching its corresponding 4-bit code (see Figure 7) into the Receive Data Register. At this point the GT
output is activated and drives v
c
to V
DD
. GT continues to drive high as long as ESt remains high. Finally, after a
4
Zarlink Semiconductor Inc.
MT8880C
Data Sheet
short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received
tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate
bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed
steering flag is active.
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the
four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to
validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together
with the capability of selecting the steering time constants externally, allows the designer to tailor performance to
meet a wide variety of system requirements.
V
DD
C1
V
DD
St/GT
ESt
R1
Vc
t
GTA
= (R1C1) In (V
DD
/ V
TSt
)
MT8880C
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen
according to the formula:
t
REC
= t
DP
+t
GTP
t
ID
=t
DA
+t
GTA
The value of t
DP
is a device parameter (see AC Electrical Characteristics) and t
REC
is the minimum signal duration
to be recognized by the receiver. A value for C1 of 0.1
µF
is recommended for most applications, leaving R1 to be
selected by the designer. Different steering arrangements may be used to select independently the guard times for
tone present (t
GTP
) and tone absent (t
GTA
). This may be necessary to meet system specifications which place both
accept and reject limits on both tone duration and interdigital pause. Guard time adjustment also allows the
designer to tailor system parameters such as talk off and noise immunity.
5
Zarlink Semiconductor Inc.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
