QUAD T1/E1 SHORT HAUL
LINE INTERFACE UNIT
FEATURES
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IDT82V2044
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Fully integrated quad T1/E1 short haul line interface which
supports 100
Ω
T1 twisted pair, 120
Ω
E1 twisted pair and 75
Ω
E1 coaxial applications
Selectable Single Rail mode or Dual Rail mode and AMI or
B8ZS/HDB3 encoder/decoder
Built-in transmit pre-equalization meets G.703 & T1.102
Selectable transmit/receive jitter attenuator meets ETSI CTR12/
13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications
SONET/SDH optimized jitter attenuator meets ITU G.783
mapping jitter specification
Digital/Analog LOS detector meets ITU G.775, ETS 300 233 and
T1.231
ITU G.772 non-intrusive monitoring for in-service testing for
any one of channel 1 to channel 3
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Low impedance transmit drivers with high-Z
Selectable hardware and parallel/serial host interface
Local, Remote and Inband Loopback test functions
Hitless Protection Switching (HPS) for 1 + 1 protection without
relays
JTAG boundary scan for board test
3.3 V supply with 5 V tolerant I/O
Low power consumption
Operating temperature range: -40
°C
to +85
°C
Available in 144-pin Thin Quad Flat Pack (TQFP) and 160-pin
Plastic Ball Grid Array (PBGA) packages
Green package options available
FUNCTIONAL BLOCK DIAGRAM
LOS
Detector
RTIPn
RRINGn
Analog
Loopback
TTIPn
TRINGn
Peak
Detector
Line
Driver
Slicer
CLK&Data
Recovery
(DPLL)
Digital
Loopback
Waveform
Shaper
Transmit
All Ones
G.772
Monitor
Clock
Generator
Control Interface
One of Four Identical Channels
LOSn
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Remote
Loopback
Jitter
Attenuator
B8ZS/
HDB3/AMI
Encoder
IBLC
Detector
AIS
Detector
TCLKn
TDn/TDPn
BPVIn/TDNn
RCLKn
RDn/RDPn
CVn/RDNn
Register
File
JTAG TAP
VDDIO
VDDT
VDDD
VDDA
OE
CLKE
MODE[2:0]
CS/JAS
TS2/SCLK/ALE/AS
TS1/RD/R/W
TS0/SDI/WR/DS
SDO/RDY/ACK
INT
LP[3:0]/D[7:0]/AD[7:0]
MC[3:0]/A[4:0]
MCLK
Figure-1 Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
2005 Integrated Device Technology, Inc.
TRST
TCK
TMS
TDI
TDO
September 22, 2005
DSC-6531/-
IDT82V2044
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
DESCRIPTION
The IDT82V2044 is a single chip, 4-channel T1/E1 short haul PCM
transceiver with a reference clock of 1.544 MHz (T1) or 2.048 MHz (E1).
The IDT82V2044 contains 4 transmitters and 4 receivers.
All the receivers and transmitters can be programmed to work either
in Single Rail mode or Dual Rail mode. B8ZS/HDB3 or AMI encoder/
decoder is selectable in Single Rail mode. Pre-encoded transmit data in
NRZ format can be accepted when the device is configured in Dual Rail
mode. The receivers perform clock and data recovery by using inte-
grated digital phase-locked loop. As an option, the raw sliced data (no
retiming) can be output on the receive data pins. Transmit equalization is
implemented with low-impedance output drivers that provide shaped
waveforms to the transformer, guaranteeing template conformance.
A jitter attenuator is integrated in the IDT82V2044 and can be
switched into either the transmit path or the receive path for all channels.
The jitter attenuation performance meets ETSI CTR12/13, ITU G.736,
G.742, G.823, and AT&T Pub 62411 specifications.
The IDT82V2044 offers hardware control mode and software control
mode. Software control mode works with either serial host interface or
parallel host interface. The latter works via an Intel/Motorola compatible
8-bit parallel interface for both multiplexed or non-multiplexed applica-
tions. Hardware control mode uses multiplexed pins to select different
operation modes when the host interface is not available to the device.
The IDT82V2044 also provides loopback and JTAG boundary scan
testing functions. Using the integrated monitoring function, the
IDT82V2044 can be configured as a 4-channel transceiver with non-
intrusive protected monitoring points.
The IDT82V2044 can be used for SDH/SONET multiplexers, central
office or PBX, digital access cross connects, digital radio base stations,
remote wireless modules and microwave transmission systems.
PIN CONFIGURATIONS
GNDIO
GNDIO
DNC
DNC
DNC
DNC
GNDIO
GNDIO
GNDIO
TDI
TDO
TCK
TMS
TRST
IC
IC
VDDIO
GNDIO
VDDA
GNDA
MODE0/CODE
CS/JAS
TS2/SCLK/ALE/AS
TS1/RD/R/W
TS0/SDI/WR/DS
SDO/RDY/ACK
INT
TCLK2
TD2/TDP2
BPVI2/TDN2
RCLK2
RD2/RDP2
CV2/RDN2
LOS2
TCLK3
TD3/TDP3
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
Description
GNDIO
GNDIO
DNC
DNC
DNC
DNC
GNDIO
GNDIO
GNDIO
MCLK
MODE2
A4
MC3/A3
MC2/A2
MC1/A1
MC0/A0
VDDIO
GNDIO
VDDD
GNDD
LP0/D0/AD0
LP1/D1/AD1
LP2/D2/AD2
LP3/D3/AD3
D4/AD4
D5/AD5
D6/AD6
D7/AD7
TCLK1
TD1/TDP1
BPVI1/TDN1
RCLK1
RD1/RDP1
CV1/RDN1
LOS1
TCLK0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GNDIO
DNC
DNC
DNC
DNC
OE
CLKE
VDDT
DNC
DNC
GNDT
DNC
DNC
GNDT
DNC
DNC
VDDT
DNC
DNC
VDDT
DNC
DNC
GNDT
DNC
DNC
GNDT
DNC
DNC
VDDT
DNC
DNC
DNC
DNC
DNC
DNC
GNDIO
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
IDT82V2044
(Top View)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
BPVI3/TDN3
RCLK3
RD3/RDP3
CV3/RDN3
LOS3
RTIP3
RRING3
VDDT
TTIP3
TRING3
GNDT
RRING2
RTIP2
GNDT
TRING2
TTIP2
VDDT
RTIP1
RRING1
VDDT
TTIP1
TRING1
GNDT
RRING0
RTIP0
GNDT
TRING0
TTIP0
VDDT
MODE1
LOS0
CV0/RDN0
RD0/RDP0
RCLK0
BPVI0/TDN0
TD0/TDP0
Figure-2 TQFP144 Package Pin Assignment
2
September 22, 2005
IDT82V2044
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
B
GNDI
O
GNDI
O
GNDI
O
VDDT
DNC
C
D
GNDI
O
GNDI
O
GNDI
O
VDDT
DNC
E
F
MC
1
MC
2
MC
3
A4
G
H
J
K
L
TCLK
1
TDP
1
TDN
1
VDDT
TTIP
1
M
RCLK
1
RDP
1
RDN
1
VDDT
TRING
1
N
TCLK
0
TDP
0
TDN
0
VDDT
TTIP
0
P
RCLK
0
RDP
0
RDN
0
VDDT
TRING
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DNC
DNC
DNC
VDDT
DNC
DNC
DNC
DNC
VDDT
DNC
MCLK
MODE
2
DNC
DNC
VDDIO VDDD
D0
MC
0
D2
D1
D6
D5
D4
D3
D7
MODE
1
LOS
1
LOS
0
GNDIO GNDD
GNDT GNDT GNDT GNDT
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
GNDT GNDT GNDT GNDT
RRING
1
RRING
2
RTIP
1
RTIP
2
RRING
0
RRING
3
RTIP
0
RTIP
3
IDT82V2044
(Bottom View)
GNDT GNDT GNDT GNDT
DNC
VDDT
DNC
DNC
DNC
A
DNC
VDDT
GNDI
O
GNDI
O
GNDI
O
B
DNC
VDDT
DNC
DNC
DNC
C
DNC
VDDT
GNDI
O
GNDI
O
GNDI
O
D
DNC
DNC
CLKE
OE
E
TMS
TDI
TDO
TCK
F
GNDIO GNDA
TRST
IC
MODE
0
IC
CS
TS
2
TS
1
TS
0
J
LOS
3
LOS
2
INT
SDO
K
GNDT GNDT GNDT GNDT
TTIP
2
VDDT
TDN
2
TDP
2
TCLK
2
L
TRING
2
VDDT
RDN
2
RDP
2
RCLK
2
M
TTIP
3
VDDT
TDN
3
TDP
3
TCLK
3
N
TRING
3
VDDT
RDN
3
RDP
3
RCLK
3
P
VDDIO VDDA
G
H
Figure-3 PBGA160 Package Pin Assignment
Pin Configurations
3
September 22, 2005
IDT82V2044
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
1
PIN DESCRIPTION
Table-1 Pin Description
Name
Type
Pin No.
TQFP144
PBGA160
Transmit and Receive Line Interface
TTIP0
TTIP1
TTIP2
TTIP3
TRING0
TRING1
TRING2
TRING3
RTIP0
RTIP1
RTIP2
RTIP3
RRING0
RRING1
RRING2
RRING3
45
52
57
64
46
51
58
63
48
55
60
67
49
54
61
66
N5
L5
L10
N10
P5
M5
M10
P10
P7
M7
M8
P8
N7
L7
L8
N8
Description
Analog
Output
TTIPn/TRINGn: Transmit Bipolar Tip/Ring for Channel 0~3
These pins are the differential line driver outputs. They will be in high-Z state if pin OE is low or the corre-
sponding pin TCLKn is low (pin OE is global control, while pin TCLKn is per-channel control). In host
mode, each pin can be in high-Z by programming a ‘1’ to the corresponding bit in register
OE
(1)
.
Analog
Input
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 0~3
These pins are the differential line receiver inputs.
Transmit and Receive Digital Data Interface
TDn: Transmit Data for Channel 0~3
When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn is
sampled into the device on the falling edges of TCLKn, and encoded by AMI or B8ZS/HDB3 line code
rules before being transmitted to the line.
BPVIn: Bipolar Violation Insertion for Channel 0~3
Bipolar violation insertion is available in Single Rail mode 2 (see
Table-2 on page 13 and Table-3 on page
14)
with AMI enabled. A low-to-high transition on this pin will make the next logic one to be transmitted on
TDn the same polarity as the previous pulse, and violate the AMI rule. This is for testing.
TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~3
When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input
on this pin. Data on TDPn/TDNn are sampled on the falling edges of TCLKn. The line code in dual rail
mode is as the follow:
TDPn
0
0
1
1
TDNn
0
1
0
1
Output Pulse
Space
Negative Pulse
Positive Pulse
Space
TD0/TDP0
TD1/TDP1
TD2/TDP2
TD3/TDP3
I
BPVI0/TDN0
BPVI1/TDN1
BPVI2/TDN2
BPVI3/TDN3
37
30
80
73
38
31
79
72
N2
L2
L13
N13
N3
L3
L12
N12
Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding
channel into Single Rail mode 1 (see
Table-2 on page 13 and Table-3 on page 14).
1
. Register name is indicated by bold capital letter. For example,
OE
indicates Output Enable Register.
Pin Description
4
September 22, 2005
IDT82V2044
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
Pin No.
TQFP144
PBGA160
Description
TCLKn: Transmit Clock for Channel 0~3
The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The
transmit data at TDn/TDPn or TDNn is sampled into the device on the falling edges of TCLKn.
Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All
Ones (TAOS) state (when MCLK is clocked). In TAOS state, the TAOS generator adopts MCLK as the
clock reference.
If TCLKn is low, the corresponding transmit channel is set into power down state, while driver output ports
become high-Z.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the fol-
lows:
TCLK0
TCLK1
TCLK2
TCLK3
36
29
81
74
N1
L1
L14
N14
MCLK
Clocked
Clocked
Clocked
Normal operation
Transmit All Ones (TAOS) signals to the line side in the corresponding
High (≥ 16 MCLK)
transmit channel.
Low (≥ 64 MCLK) The corresponding transmit channel is set into power down state.
TCLKn is clocked Normal operation
Transmit All Ones (TAOS) signals to the line side
TCLKn is high
in the corresponding transmit channel.
(≥ 16 TCLK1)
Corresponding transmit channel is set into power
TCLKn is low
TCLK1 is clocked
down state.
(≥ 64 TCLK1)
The receive path is not affected by the status of TCLK1. When MCLK
is high, all receive paths just slice the incoming data stream. When
MCLK is low, all the receive paths are powered down.
TCLK1 is unavail-
All four transmitters (TTIPn & TRINGn) will be in high-Z.
able.
TCLKn
Clocked
Transmit Mode
I
High/Low
High/Low
RDn: Receive Data for Channel 0~3
In Single Rail mode, the received NRZ data is output on this pin. The data is decoded by AMI or B8ZS/
HDB3 line code rule.
CVn: Code Violation for Channel 0~3
In Single Rail mode, the bipolar violation, code violation and excessive zeros will be reported by driving pin
CVn high for a full clock cycle. However, only bipolar violation is indicated when AMI decoder is selected.
RDPn/RDNn: Positive/Negative Receive Data for Channel 0~3
In Dual Rail Mode with clock recovery, these pins output the NRZ data. A high signal on RDPn indicates
the receipt of a positive pulse on RTIPn/RRINGn while a high signal on RDNn indicates the receipt of a
negative pulse on RTIPn/RRINGn.
The output data at RDn or RDPn/RDNn are clocked out on the falling edges of RCLK when the CLKE input
is low, or are clocked out on the rising edges of RCLK when CLKE is high.
In Dual Rail Mode without clock recovery, these pins output the raw RZ sliced data. In this data recovery
mode, the active polarity of RDPn/RDNn is determined by pin CLKE. When pin CLKE is low, RDPn/RDNn
is active low. When pin CLKE is high, RDPn/RDNn is active high.
In hardware mode, RDn or RDPn/RDNn will remain active during LOS. In host mode, these pins will either
remain active or insert alarm indication signal (AIS) into the receive path, determined by bit AISE in regis-
ter
GCF.
RDn or RDPn/RDNn is set into high-Z when the corresponding receiver is powered down.
RD0/RDP0
RD1/RDP1
RD2/RDP2
RD3/RDP3
CV0/RDN0
CV1/RDN1
CV2/RDN2
CV3/RDN3
O
High-Z
40
33
77
70
41
34
76
69
P2
M2
M13
P13
P3
M3
M12
P12
Pin Description
5
September 22, 2005
PCB设计
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