Virtex-5 FPGA
Configuration User
Guide
UG191 (v3.12) May 8, 2017
R
R
Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising
under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or
consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action
brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product
specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are
subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos;
IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx
products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and
liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos.
© 2006–2012, 2017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included
herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
Revision History
The following table shows the revision history for this document.
Date
04/14/2006
05/12/2006
Version
1.0
1.1
Revision
Initial Xilinx release.
Minor typographical edits to entire document to improve clarity.
Chapter 1: Revised
Table 1-1, Table 1-2, Table 1-9, Table 1-11.
Chapter 2: Clarified bit-swapping (Byte Swap rule) throughout. Updated
“Page Mode
Support,” page 71.
Chapter 8: Added new section called
“MultiBoot Bitstream Spacing,” page 155.
Chapter 9: Added
“Post_CRC Constraints”
section.
Virtex-5 FPGA Configuration Guide
www.xilinx.com
UG191 (v3.12) May 8, 2017
Date
07/31/2006
Version
1.2
Chapter 1:
Revision
•
Moved
“Configuration Data File Formats”
and
“Generating PROM Files”
from
Chapter 2, and
“Bitstream Overview”from
Chapter 6 into this chapter to consolidate
all the data configuration file information.
•
Updated sentence in“Device
Power-Up (Step 1),” page 24
to say “
All dedicated
input pins operate at V
CC_CONFIG
LVCMOS level. “
•
Moved
“Packet Types”
section from Chapter 1 to Chapter 6.
•
Moved
“Bit Swapping”
and
“Parallel Bus Bit Order”
sections under
“Generating
PROM Files”
section.
•
Created
“Configuration Sequence”
header and moved
“Setup (Steps 1-3),” “Bitstream
Loading (Steps 4-7),”
and
“Startup (Step 8)”
sections under it.
Chapter 2:
•
Added Note 2 to
Table 2-1.
Revised RCMD in
Table 2-8.
•
Moved
“Board Layout for Configuration Clock (CCLK)”
to after
“Byte Peripheral
Interface Parallel Flash Mode.”
•
Replaced Clock Management Technology (CMT) with Digital Clock Managers (DCM)
throughout user guide.
Chapter 7:
•
Revised the paragraph above
Table 7-9.
09/06/2006
10/12/2006
2.0
2.1
Updated
Table 1-2, Table 1-4,
and
Table 1-13.
Chapter 1: Added XC5VLX85T information to
Table 1-4
and
Table 1-13.
Updated the
Program Latency value in Table 1-10. Updated the Program Latency value in
Table 1-10.
Chapter 3: Updated the V
CCINT
value in
Figure 3-6.
Chapter 6: Updated
Figure 6-1
and
Table 6-7
to include system monitor pin information.
Chapter 9: Added partial reconfiguration application information to
Chapter 9,
“Readback CRC.”
02/01/2007
2.2
Updated
Table 1-4, page 18
(added LX220T and SXT devices),
Table 1-13, page 29
(added
LX220T and SXT devices),
“ABORT Status Word,” page 59, Table 6-5, page 113
(CBC
value),
“Configuration Memory Read Procedure (SelectMAP),” page 138
(steps 13 and
14), and
Table 6-8, page 118
(block type).
Updated:
Figure 2-3,
notes relevant to
Figure 2-4, “Guidelines and Design
Considerations for Serial Daisy Chains,”
notes related to
Figure 2-21
and
Figure 2-22,
“Configuration Memory Frames”
(including
Table 6-1), Table 6-10, Figure 6-9,
“Configuration Memory Read Procedure (SelectMAP),” Table 7-2,
and
Table 7-6.
General: Updated PROG_B to PROGRAM_B throughout user guide.
Chapter 1: Updated
“Check Device ID (Step 5)”
section, including
Table 1-13.
Chapter 2: Updated
Figure 2-13.
Chapter 3: Updated
Table 3-3,
added state descriptions for TAP controller.
Chapter 4: Updated
“STARTUP_VIRTEX5”
section.
10/10/2007
2.5
Chapter 1: Updated
“Configuration Modes and Pins.”
Chapter 2: Updated
Figure 2-17
and
“Serial Daisy Chains”
and
“SelectMAP
Reconfiguration”
sections.
Chapter 4: Updated
Table 4-3.
Chapter 5: Updated
“Changing the Multiply and Divide Values.”
Chapter 6: Updated
Table 6-7.
Chapter 7: Updated
Table 7-1
and relevant text. Updated
Table 7-2.
07/05/2007
2.3
07/31/2007
2.4
UG191 (v3.12) May 8, 2017
www.xilinx.com
Virtex-5 FPGA Configuration Guide
Date
12/11/2007
Version
2.6
Revision
Updated legal disclaimer and copyright information.
Chapter 1: Updated
Table 1-3, Table 1-4, Table 1-10,
and
Table 1-13.
Chapter 2: Updated notes that are relevant to
Figure 2-22
and
Table 2-9.
Chapter 4: Updated the
“ICAP_VIRTEX5”
section.
Chapter 6: Updated
Table 6-1.
Chapter 8: Updated section name from Fallback Reconfiguration to
“Fallback
MultiBoot.”
02/01/2008
2.7
Minor text edits throughout user guide.
Chapter 1: Updated
the M2, M1, and M0 mode pins setting information in
“Configuration Modes and Pins.”
Also updated the
“Device Power-Up (Step 1)”
section.
Chapter 2: Updated
Figure 2-23.
Chapter 3: Updated the
“Boundary-Scan for Virtex-5 Devices Using IEEE Standard
1149.1”
section.
03/31/2008
3.0
Updated Preface.
Added FXT devices.
Chapter 1: Updated
Table 1-3
and
Table 1-13.
Chapter 3: Updated the
“Boundary-Scan for Virtex-5 Devices Using IEEE Standard
1149.1”
and
“Instruction Register”sections.
Updated
Table 3-2
and
Table 3-3.
Chapter 6: Updated
Table 6-1.
04/25/2008
3.1
Chapter 1: Updated
Table 1-4
and
Table 1-13.
Chapter 2: Updated
“SelectMAP Reconfiguration”
and notes pertaining to
Figure 2-22,
page 67.
Chapter 6: Updated
Table 6-1
and
“Block RAM Contents.”
Chapter 7: Updated
Table 7-3.
07/11/2008
3.2
Chapter 1: Updated
Table 1-4
notes,
“PROM Files for SelectMAP Configuration,”
and
“Power-On Sequence Precautions.”
Chapter 2: Added the
“High-Performance Platform Flash XL SelectMAP Configuration”
section, including
Figure 2-7
and
Figure 2-8,
and
“Power-On Sequence Precautions.”
Updated:
Figure 2-5
and
Figure 2-9.
Updated notes related to
Figure 2-3, Figure 2-4,
Figure 2-9, Figure 2-13,
and
Figure 2-20.
Updated
“Byte Peripheral Interface Parallel
Flash Mode,”
including
Figure 2-22
and related notes.
Chapter 3: Updated
Table 3-4.
Chapter 4: Updated
Table 4-4.
Chapter 6: Updated
Table 6-1, Table 6-11.
Chapter 8: Updated
“Fallback Overview.”
09/03/2008
3.3
Chapter 1: Updated
“Loading the Encryption Key,”
Chapter 3: Updated
Table 3-3.
Chapter 4: Updated
“FRAME_ECC_VIRTEX5.”
Chapter 5: Updated
Table 5-2.
Chapter 6: Updated
“Command Register (CMD).”
Chapter 9: Updated introductory paragraphs in
“Readback CRC,”
and
“Post_CRC
Constraints.”
Virtex-5 FPGA Configuration Guide
www.xilinx.com
UG191 (v3.12) May 8, 2017
Date
09/23/2008
Version
3.4
Revision
Chapter 1: Added the TXT platform to
Table 1-4, Table 1-13.
Chapter 2: Updated
Figure 2-9, Figure 2-12
and
Figure 2-15.
Chapter 6: Added the TXT platform to
Table 6-1.
10/29/2008
3.5
Chapter 2: Updated notes on
Figure 2-9.
Chapter 4: Updated
“STARTUP_VIRTEX5.”
Chapter 8: Added cross reference to
“IPROG Embedded in the Bitstream.”
02/11/2009
3.6
Chapter 1: Updated
Table 1-2
and the
“Sample Mode Pins (Step 3)”
section.
Chapter 2: Updated notes relating toFigure
2-22.
Chapter 3: Updated the
“Multiple Device Configuration”section.
Chapter 6: Updated
Table 6-8.
Updated ISC_PROGRAM_SECURITY to ISC_PROGRAM_KEY.
06/24/2009
3.7
Chapter 1: Updated
Table 1-3
to indicate the
BIN
file format is bit swapped. Updated
Table 1-5
by changing the bit order of the data words defined in the header for each row.
Updated first paragraph, fourth sentence in
“Bit Swapping”.
Chapter 4: Updated definition of O[31:0] pin in
Table 4-3.
Chapter 6: Removed CRCC command from
Table 6-6.
Chapter 7: Updated step 9 of
“Configuration Memory Read Procedure (SelectMAP).”
Added “NOOP Omitted” label to
Figure 7-2.
Updated
Table 7-2
to conform to changes
in
“Configuration Memory Read Procedure (SelectMAP).”
08/14/2009
3.8
Chapter 1: Added new paragraph to
“Bus Width Auto Detection”
with an example of the
Sync word bit order at the FPGA pins. Updated
Table 1-5
by changing the bit order of the
data words defined in the header for each row. Updated first paragraph in
“Sync Word.”
Chapter 4: Updated the ECCERROR and the SYNDROME[11:0] descriptions in
Table 4-4.
Chapter 6: Updated
Table 6-6
by replacing the Reserved command with the CRCC
command.
Chapter 7: Updated
“Configuration Register Read Procedure (SelectMAP)”
step 1 and
step 3. Updated
“Configuration Memory Read Procedure (SelectMAP)”
step 8 and the
last paragraph. Updated step 9 in
Table 7-2.
Updated Note 1 in
Table 7-3.
Chapter 9: Updated the
Readback CRC logic running conditions in the second
paragraph under
“Readback CRC.”
08/03/2010
3.9
Updated
Table 1-3
to indicate that BIN is not bit swapped with the BitGen tool, but is bit
swapped with the PROMGen tool. Corrected the order of rows in
Table 1-16
(placed
phase 4 row above phase 5 row). Updated
Figure 1-12
(timing of GWE and GTS).
Changed “the external configuration interfaces” to “any configuration interface” in the
first sentence of the fourth paragraph under
“Loading Encrypted Bitstreams”.
Updated
Figure 2-12
by adding PROG inputs to the three FPGA devices. Added Note 10 to
“
Notes relevant to
Figure 2-12”.
Added second sentence about
the persist option
selection
to second paragraph under
“SelectMAP Reconfiguration”.
Added sentence
to definitions of DEN and DWE in
Table 5-1
indicating that they should only be
pulsed for one DCLK cycle. Updated description of
START_ADDR in
Table 6-12.
Updated
Table 6-15
(inserted three rows). Updated second paragraph under
“Fallback Overview”
indicating that indirect BPI programming is supported with
iMPACT version 11.3 and later when using the RS pin. Added sentence to first
paragraph in
Chapter 9, “Readback CRC”
indicating that if a CRC error is detected,
the device must be reconfigured.
08/20/2010
3.9.1
Fixed corrupt file.
UG191 (v3.12) May 8, 2017
www.xilinx.com
Virtex-5 FPGA Configuration Guide
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
