52
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
General Description
Virtex®-6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized
ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1
slices, enhanced mixed-mode clock management blocks, PCI Express® (GEN 1) compatible integrated blocks, a tri-mode
Ethernet media access controller (MAC), up to 241K logic cells, and strong IP support. Using the third generation ASMBL™
(Advanced Silicon Modular Block) column-based architecture, the Virtex-6 CXT family also contains SelectIO™ technology
with built-in digitally controlled impedance, ChipSync™ source-synchronous interface blocks, enhanced mixed-mode clock
management blocks, and advanced configuration options. Customers needing higher transceiver speeds, greater I/O
performance, additional Ethernet MACs, or greater capacity should instead use the Virtex-6 LXT or SXT families. Built on a
40 nm state-of-the-art copper process technology, Virtex-6 CXT FPGAs are a programmable alternative to custom ASIC
technology. Virtex-6 CXT FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver
integrated software and hardware components to enable designers to focus on innovation as soon as their development
cycle begins.
Summary of Virtex-6 CXT FPGA Features
•
Advanced, high-performance, FPGA Logic
•
Real 6-input look-up table (LUT) technology
•
Dual LUT5 (5-input LUT) option
•
LUT/dual flip-flop pair for applications requiring rich
register mix
•
Improved routing efficiency
•
64-bit (or 32 x 2-bit) distributed LUT RAM option
•
SRL32/dual SRL16 with registered outputs option
Powerful mixed-mode clock managers (MMCM)
•
MMCM blocks provide zero-delay buffering, frequency
synthesis, clock-phase shifting, input-jitter filtering, and
phase-matched clock division
36-Kb block RAM/FIFOs
•
Dual-port RAM blocks
•
Programmable
-
Dual-port widths up to 36 bits
-
Simple dual-port widths up to 72 bits
•
Enhanced programmable FIFO logic
•
Built-in optional error-correction circuitry
•
Optionally use each block as two independent 18 Kb
blocks
High-performance parallel SelectIO technology
•
1.2 to 2.5V I/O operation
•
Source-synchronous interfacing using
ChipSync™ technology
•
Digitally controlled impedance (DCI) active termination
•
Flexible fine-grained I/O banking
•
High-speed memory interface support with integrated
write-leveling capability
•
Advanced DSP48E1 slices
•
25 x 18, two's complement multiplier/accumulator
•
Optional pipelining
•
New optional pre-adder to assist filtering applications
•
Optional bitwise logic functionality
•
Dedicated cascade connections
Flexible configuration options
•
SPI and Parallel Flash interface
•
Multi-bitstream support with dedicated fallback
reconfiguration logic
•
Automatic bus width detection
Integrated interface blocks for PCI Express designs
•
Compliant to the PCI Express Base Specification 2.0
•
Gen1 Endpoint (2.5 Gb/s) support with GTX transceivers
•
x1, x2, x4, or x8 lane support per block
•
One virtual channel, eight traffic classes
GTX transceivers: 150 Mb/s to 3.75 Gb/s
Integrated 10/100/1000 Mb/s Ethernet MAC block
•
Supports 1000BASE-X PCS/PMA and SGMII using
GTX transceivers
•
Supports MII, GMII, and RGMII using SelectIO
technology resources
40 nm copper CMOS process technology
1.0V core voltage
Two speed grades (-1 and -2)
Two temperature grades (commercial and industrial)
High signal-integrity flip-chip packaging available in standard
or Pb-free package options
Compatibility across sub-families: CXT, LXT, and SXT
devices are footprint compatible in the same package
•
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© 2009–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS153 (v1.6) February 11, 2011
Product Specification
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1
Virtex-6 CXT Family Data Sheet
Virtex-6 CXT FPGA Feature Summary
Table 1:
Virtex-6 CXT FPGA Feature Summary by Device
Configurable Logic
Blocks (CLBs)
Device
Logic
Cells
Slices
(1)
Max
Distributed
RAM (Kb)
DSP48E1
Slices
(2)
Block RAM Blocks
MMCMs
(4)
18 Kb
(3)
36 Kb
Max (Kb)
Interface
Maximum
Ethernet
Blocks for
GTX
MACs
(5)
PCI Express
Transceivers
Total
I/O
Banks
(6)
Max
User
I/O
(7)
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
74,496
128,000
199,680
241,152
11,640
20,000
31,200
37,680
1,045
1,740
3,040
3,650
288
480
640
768
312
528
688
832
156
264
344
416
5,616
9,504
12,384
14,976
6
10
10
12
1
2
2
2
1
1
1
1
12
16
16
16
9
15
15
18
360
600
600
600
Notes:
1.
2.
3.
4.
5.
6.
7.
Each Virtex-6 CXT FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs.
Each DSP48E1 slice contains a 25 x 18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18 Kb blocks.
Each CMT contains two mixed-mode clock managers (MMCM).
This table lists individual Ethernet MACs per device.
Does not include configuration Bank 0.
This number does not include GTX transceivers.
Virtex-6 CXT FPGA Device-Package Combinations and Maximum I/Os
Virtex-6 CXT FPGA package combinations with the maximum available I/Os per package are shown in
Table 2.
Table 2:
Virtex-6 CXT FPGA Device-Package Combinations and Maximum Available I/Os
Package
Size (mm)
Device
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
GTs
8 GTXs
8 GTXs
FF484
FFG484
23 x 23
I/O
240
240
GTs
12 GTXs
12 GTXs
12 GTXs
12 GTXs
FF784
FFG784
29 x 29
I/O
360
400
400
400
16 GTXs
16 GTXs
16 GTXs
600
600
600
GTs
FF1156
FFG1156
35 x 35
I/O
Notes:
1.
Flip-chip packages are also available in Pb-Free versions (FFG).
Virtex-6 CXT FPGA Ordering Information
The Virtex-6 CXT FPGA ordering information shown in
Figure 1
applies to all packages including Pb-Free.
X-Ref Target - Figure 1
Example: XC6VCX240T-1FFG1156C
Device Type
Speed
Grade
(-1, -2)
Temperature Range:
C = Commercial (T
J
= 0°C to +85°C)
I = Industrial (T
J
= –40°C to +100°C)
Number of Pins
Pb-Free
Package Type
DS153_01_062109
Figure 1:
Virtex-6 CXT FPGA Ordering Information
DS153 (v1.6) February 11, 2011
Product Specification
www.xilinx.com
2
Virtex-6 CXT Family Data Sheet
Virtex-6 CXT FPGA Documentation
In addition to the data sheet information found herein, complete and up-to-date documentation of the Virtex-6 family of
FPGAs is available on the Xilinx website and available for download:
Virtex-6 FPGA Configuration Guide
(UG360)
This all-encompassing configuration guide includes
chapters on configuration interfaces (serial and parallel),
multi-bitstream management, bitstream encryption,
boundary-scan and JTAG configuration, and reconfiguration
techniques.
Virtex-6 FPGA SelectIO Resources User Guide
(UG361)
This guide describes the SelectIO™ resources available in
all the Virtex-6 CXT devices.
Virtex-6 FPGA Clocking Resources User Guide
(UG362)
This guide describes the clocking resources available in all
the Virtex-6 CXT devices, including the MMCM and clock
buffers.
Virtex-6 FPGA Memory Resources User Guide
(UG363)
This guide describes the Virtex-6 CXT device block RAM
and FIFO capabilities.
Virtex-6 FPGA CLB User Guide
(UG364)
This guide describes the capabilities of the configurable
logic blocks (CLB) available in all Virtex-6 CXT devices.
Virtex-6 FPGA DSP48E1 Slice User Guide
(UG369)
This guide describes the architecture of the DSP48E1 slice
in Virtex-6 CXT FPGAs and provides configuration
examples.
Virtex-6 FPGA Packaging and Pinout Specifications
(UG365)
These specifications includes the tables for device/package
combinations and maximum I/Os, pin definitions, pinout
tables, pinout diagrams, mechanical drawings, and thermal
specifications of the Virtex-6 LXT and SXT families.
Reference these specifications when considering device
migration to the Virtex-6 LXT and SXT families.
Virtex-6 FPGA GTX Transceivers User Guide
(UG366)
This guide describes the GTX transceivers available in all
the Virtex-6 CXT FPGAs.
Virtex-6 FPGA Tri-Mode Ethernet MAC User Guide
(UG368)
This guide describes the dedicated tri-mode Ethernet
media access controller (TEMAC) available in all the
Virtex-6 CXT FPGAs.
Virtex-6 FPGA Data Sheet: DC and Switching
Characteristics
(DS152)
Reference this data sheet when considering device
migration to the Virtex-6 LXT and SXT families. It contains
the DC and Switching Characteristic specifications
specifically for the Virtex-6 LXT and SXT families.
Configuration Bitstream Overview for CXT Devices
This section contains two tables similar to those in the
Virtex-6 FPGA Configuration Guide
only updated for the CXT family.
The Virtex-6 CXT FPGA bitstream contains commands to the FPGA configuration logic as well as configuration data.
Table 3
gives a typical bitstream length and
Table 4
gives the specific device ID codes for the Virtex-6 CXT devices.
Table 3:
Virtex-6 CXT FPGA Bitstream Length
Device
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
Table 4:
Virtex-6 CXT FPGA Device ID Codes
Device
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
Total Number of Configuration Bits
26,239,328
43,719,776
61,552,736
73,859,552
ID Code (Hex)
0x042C4093
0x042CA093
0x042CC093
0x042D0093
DS153 (v1.6) February 11, 2011
Product Specification
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3
Virtex-6 CXT Family Data Sheet
CLB Overview for CXT Devices
Table 5,
updated specifically for the CXT family from a similar table in the
Virtex-6 FPGA CLB User Guide,
shows the
available resources in all Virtex-6 CXT FPGA CLBs.
Table 5:
Virtex-6 CXT FPGA Logic Resources Available in All CLBs
Device
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
Total
Slices
11,640
20,000
31,200
37,680
SLICELs SLICEMs
7,460
13,040
19,040
23,080
4,180
6,960
12,160
14,600
Number of
6-Input LUTs
46,560
80,000
124,800
150,720
Maximum
Distributed RAM (Kb)
1045
1740
3140
3770
Shift
Register (Kb)
522.5
870
1570
1885
Number of
Flip-Flops
93,120
160,000
249,600
301,440
Regional Clock Management for CXT Devices
Table 6,
updated from the
Virtex-6 FPGA Clocking Resources User Guide
specifically for the CXT family, shows the number
of clock regions in all Virtex-6 CXT FPGA CLBs.
Table 6:
Virtex-6 CXT FPGA Clock Regions
Device
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
Number of Clock Regions
6
10
10
12
CXT Packaging Specifications
Table 7,
updated from the
Virtex-6 FPGA Packaging and Pinout Specifications
specifically for the CXT family, shows the
number of GTX transceiver I/O channels.
Table 8
shows the number of available I/Os and the number of differential I/O pairs
for each Virtex-6 device/package combination.
Table 7:
Number of Serial Transceivers (GTs) I/O Channels/Device
I/O
Channels
MGTRXP
MGTRXN
MGTTXP
MGTTXN
Notes:
1.
2.
3.
4.
The XC6VCX75T has 8 GTX I/O channels in the FF484/FFG484 package and 12 GTX I/O channels in the FF784/FFG784 package.
The XC6VCX130T has 8 GTX I/O channels in the FF484/FFG484 package, 12 GTX I/O channels in the FF784/FFG784 package, and 16
GTX I/O channels in the FF1156/FFG1156 package.
The XC6VCX195T has 12 GTX I/O channels in the FF784/FFG784 package and 16 GTX I/O channels in the FF1156/FFG1156 package.
The XC6VCX240T has 12 GTX I/O channels in the FF784/FFG784 package and 16 GTX I/O channels in the FF1156/FFG1156 package.
Device
CX75T
(1)
8 or 12
8 or 12
8 or 12
8 or 12
CX130T
(2)
8, 12, or 16
8, 12, or 16
8, 12, or 16
8, 12, or 16
CX195T
(3)
12 or 16
12 or 16
12 or 16
12 or 16
CX240T
(4)
12 or 16
12 or 16
12 or 16
12 or 16
DS153 (v1.6) February 11, 2011
Product Specification
www.xilinx.com
4
Virtex-6 CXT Family Data Sheet
Table 8:
Available I/O Pin/Device/Package Combinations
Virtex-6
CXT
Device
Virtex-6 CXT FPGA Package
User I/O Pins
FF484
Available User I/Os
XC6VCX75T
Differential I/O Pairs
Available User I/Os
XC6VCX130T
Differential I/O Pairs
Available User I/Os
XC6VCX195T
Differential I/O Pairs
Available User I/Os
XC6VCX240T
Differential I/O Pairs
–
–
–
FF784
360
180
400
200
400
200
400
200
FF1156
–
–
240
120
240
120
–
600
300
600
300
600
300
GTX Transceivers in CXT Devices
CXT devices have between 8 to 16 gigabit transceiver circuits. Each GTX transceiver is a combined transmitter and receiver
capable of operating at a data rate between 480 Mb/s and 3.75 Gb/s. Lower data rates can be achieved using FPGA logic-
based oversampling. The transmitter and receiver are independent circuits that use separate PLLs to multiply the reference
frequency input by certain programmable numbers between 2 and 25, to become the bit-serial data clock. Each GTX
transceiver has a large number of user-definable features and parameters. All of these can be defined during device
configuration, and many can also be modified during operation.
DS153 (v1.6) February 11, 2011
Product Specification
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