74LVC1G384-Q100
Bilateral switch
Rev. 1 — 19 February 2013
Product data sheet
1. General description
The 74LVC1G384-Q100 provides one single pole, single throw analog switch function. It
has two input/output terminals (Y and Z) and an active LOW enable input pin (E). When
pin E is HIGH, the analog switch is turned off.
Schmitt trigger action at the enable input makes the circuit tolerant of slower input rise and
fall times across the entire V
CC
range from 1.65 V to 5.5 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5
(typical) at V
CC
= 2.7 V
6.5
(typical) at V
CC
= 3.3 V
6
(typical) at V
CC
= 5 V
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Switch current capability of 32 mA
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD 78 Class I
Enable input accepts voltages up to 5.5 V
Inputs accept voltages up to 5 V
Multiple package options
NXP Semiconductors
74LVC1G384-Q100
Bilateral switch
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74LVC1G384GW-Q100
74LVC1G384GV-Q100
Name
Description
Version
SOT353-1
SOT753
Type number
40 C
to +125
C
TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
40 C
to +125
C
SC-74A
plastic surface-mounted package; 5 leads
4. Marking
Table 2.
Marking
Marking code
[1]
YL
YL
Type number
74LVC1G384GW-Q100
74LVC1G384GV-Q100
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
E
Z
Y
001aag476
1
1
X1
001aaa373
2
4 #
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Z
Y
E
V
CC
001aaa372
Fig 3.
Logic diagram
74LVC1G384_100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 19 February 2013
2 of 21
NXP Semiconductors
74LVC1G384-Q100
Bilateral switch
6. Pinning information
6.1 Pinning
/9&*4
<
=
*1'
DDD
9&&
(
Fig 4.
Pin configuration SOT353-1 and SOT753
6.2 Pin description
Table 3.
Symbol
Y
Z
GND
E
V
CC
Pin description
Pin
1
2
3
4
5
Description
independent input or output
independent output or input
ground (0 V)
enable input (active LOW)
supply voltage
7. Functional description
Table 4.
Input E
L
H
[1]
H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Switch
ON-state
OFF-state
74LVC1G384_100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 19 February 2013
3 of 21
NXP Semiconductors
74LVC1G384-Q100
Bilateral switch
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
SK
V
SW
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
input clamping current
switch clamping current
switch voltage
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
0.5
0.5
50
-
[2]
Max
+6.5
+6.5
-
50
V
CC
+ 0.5
50
100
-
+150
250
Unit
V
V
mA
mA
V
mA
mA
mA
C
mW
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
enable and disable mode
V
SW
>
0.5
V or V
SW
< V
CC
+ 0.5 V
0.5
-
-
100
65
T
amb
=
40
C to +125
C
[3]
-
The minimum input voltage rating may be exceeded if the input current rating is observed.
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
For TSSOP5 and SC-74A packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and
fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
[1]
Conditions
Min
1.65
0
0
40
-
-
Typ
-
-
-
-
-
-
Max
5.5
5.5
V
CC
+125
20
10
Unit
V
V
V
C
ns/V
ns/V
[1]
To avoid sinking GND current from terminal Z when switch current flows in terminal Y, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current flows from terminal Y. In this case, there is no limit for
the voltage drop across the switch.
74LVC1G384_100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 19 February 2013
4 of 21
NXP Semiconductors
74LVC1G384-Q100
Bilateral switch
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
I
I
I
S(OFF)
input leakage
current
OFF-state
leakage
current
ON-state
leakage
current
pin E; V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
V
CC
= 5.5 V; see
Figure 5
[2]
40 C
to +85
C
Min
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
0.1
0.1
Max
-
-
-
-
0.35V
CC
0.7
0.8
0.3V
CC
5
5
40 C
to +125
C
Min
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
-
-
Max
-
-
-
-
0.7
0.8
0.3V
CC
100
200
Unit
V
V
V
V
V
V
V
A
A
0.35V
CC
V
[2]
I
S(ON)
V
CC
= 5.5 V; see
Figure 6
[2]
-
0.1
5
-
200
A
I
CC
supply current V
I
= 5.5 V or GND;
V
SW
= GND or V
CC
; V
CC
= 1.65 V
to 5.5 V
additional
pin E; V
I
= V
CC
0.6 V;
supply current V
SW
= GND or V
CC
; V
CC
= 5.5 V
input
capacitance
OFF-state
capacitance
ON-state
capacitance
[2]
-
0.1
10
-
200
A
I
CC
C
I
C
S(OFF)
C
S(ON)
[2]
-
-
-
-
5
2.0
5.0
9.5
500
-
-
-
-
-
-
-
5000
-
-
-
A
pF
pF
pF
[1]
[2]
All typical values are measured at T
amb
= 25
C.
These typical values are measured at V
CC
= 3.3 V.
74LVC1G384_100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 19 February 2013
5 of 21