i960
®
VH Embedded-PCI Processor
Preliminary
Datasheet
Product Features
s
s
s
s
High Performance 80960JT Core
— Sustained One Instruction/Clock
Execution
— 16 Kbyte Two-Way Set-Associative
Instruction Cache
— 4 Kbyte Direct-Mapped Data Cache
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— Programmable Bus Widths:
8-, 16-, 32-Bit
— 1 Kbyte Internal Data RAM
— Local Register Cache
(Eight Available Stack Frames)
— Two 32-Bit On-Chip Timer Units
— Core Clock Rate: 1x, 2x or 3x Local Bus
Clock
PCI Interface
— Complies with PCI Local Bus
Specification 2.2
— Runs at Local Bus Clock Rate
— 5 Volts PCI Signaling Environment
Address Translation Unit
— Connects Local Bus to PCI Bus
— Inbound/Outbound Address Translation
Support
— Direct Outbound Addressing Support
Messaging Unit
— Four Message Registers
— Two Doorbell Registers
s
s
s
s
s
Memory Controller
— 256 Mbytes of 32- or 36-Bit DRAM
— Interleaved or Non-Interleaved DRAM
— Fast Page-Mode DRAM Support
— Extended Data Out DRAM Support
— Two Independent Banks for SRAM /
ROM / Flash (16 Mbytes/Bank; 8- or
32-Bit)
DMA Controller
— Two Independent Channels
— PCI Memory Controller Interface
— 32-Bit Local Bus Addressing
— 64-Bit PCI Bus Addressing
— Independent Interface to PCI Bus
— 132 Mbyte/sec Burst Transfers to PCI
and Local Buses
— Direct Addressing to and from PCI
Buses
— Unaligned Transfers Supported in
Hardware
— Channels Dedicated to PCI Bus
I
2
C Bus Interface Unit
— Serial Bus
— Master/Slave Capabilities
— System Management Functions
3.3 V Supply
— 5 V Tolerant Inputs
— TTL Compatible Outputs
Plastic BGA* Package
— 324 Ball-Grid Array (PBGA)
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 273179-004
April 1999
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The i960
®
VH Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1999
*Third-party brands and names are the property of their respective owners.
Preliminary
Datasheet
80960VH
Contents
1.0
About This Document......................................................................................................... 7
1.1
1.2
1.3
2.0
Solutions960
®
Program......................................................................................... 7
Terminology........................................................................................................... 7
Additional Information Sources ............................................................................. 7
Functional Overview........................................................................................................... 8
2.1
Key Functional Units ............................................................................................. 9
2.1.1 DMA Controller......................................................................................... 9
2.1.2 Address Translation Unit .......................................................................... 9
2.1.3 Messaging Unit......................................................................................... 9
2.1.4 Memory Controller.................................................................................... 9
2.1.5 Core and Peripheral Unit.......................................................................... 9
2.1.6 I2C Bus Interface Unit .............................................................................. 9
i960
®
Core Features (80960JT) .......................................................................... 10
2.2.1 Burst Bus................................................................................................ 11
2.2.2 Timer Unit ............................................................................................... 11
2.2.3 Priority Interrupt Controller ..................................................................... 11
2.2.4 Faults and Debugging ............................................................................ 11
2.2.5 On-Chip Cache and Data RAM .............................................................. 12
2.2.6 Local Register Cache ............................................................................. 12
2.2.7 Test Features ......................................................................................... 12
2.2.8 Memory-Mapped Control Registers ....................................................... 12
2.2.9 Instructions, Data Types and Memory Addressing Modes .....................13
2.2
3.0
Package Information ........................................................................................................15
3.1
Package Introduction........................................................................................... 15
3.1.1 Functional Signal Definitions ..................................................................15
3.1.2 324-Lead PBGA Package ...................................................................... 25
Package Thermal Specifications .........................................................................33
3.2.1 Thermal Specifications ........................................................................... 33
3.2.1.1 Ambient Temperature................................................................ 33
3.2.1.2 Case Temperature .................................................................... 33
3.2.1.3 Thermal Resistance ..................................................................34
3.2.2 Thermal Analysis .................................................................................... 34
3.2
4.0
Electrical Specifications.................................................................................................... 35
4.1
4.2
4.3
4.4
V
CC5
Pin Requirements (V
DIFF
) .......................................................................... 35
V
CCPLL
Pin Requirements ................................................................................... 36
DC Specifications ................................................................................................ 37
AC Specifications ................................................................................................ 39
4.4.1 Relative Output Timings .........................................................................41
4.4.2 Memory Controller Relative Output Timings .......................................... 41
4.4.3 Boundary Scan Test Signal Timings ...................................................... 43
4.4.4 I2C Interface Signal Timings ..................................................................44
AC Test Conditions ............................................................................................. 44
AC Timing Waveforms ........................................................................................ 45
Memory Controller Output Timing Waveforms ....................................................48
4.5
4.6
4.7
Preliminary
Datasheet
3
80960VH
5.0
6.0
Bus Functional Waveforms .............................................................................................. 54
Device Identification On Reset ......................................................................................... 63
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Product Name Functional Block Diagram ............................................................. 8
80960JT Core Block Diagram ............................................................................. 10
324-Plastic Ball Grid Array Top and Side View ................................................... 25
324-Plastic Ball Grid Array (Top View)................................................................ 26
Thermocouple Attachment .................................................................................. 33
V
CC5
Current-Limiting Resistor ........................................................................... 36
V
CCPLL
Lowpass Filter ........................................................................................ 36
AC Test Load ...................................................................................................... 44
P_CLK, TCLK Waveform .................................................................................... 45
T
OV
Output Delay Waveform .............................................................................. 45
T
OF
Output Float Waveform................................................................................ 46
T
IS
and T
IH
Input Setup and Hold Waveform ...................................................... 46
T
LXL
and T
LXA
Relative Timings Waveform ........................................................ 46
DT/R# and DEN# Timings Waveform ................................................................. 47
I
2
C Interface Signal Timings................................................................................ 47
Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960
Local Bus ............................................................................................................ 48
Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960
Local Bus ............................................................................................................ 49
FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States.................. 50
FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States .................. 51
EDO DRAM, Read Cycle .................................................................................... 52
EDO DRAM, Write Cycle .................................................................................... 52
32-Bit Bus, SRAM Read Accesses with 0 Wait States ....................................... 53
32-Bit Bus, SRAM Write Accesses with 0 Wait States........................................ 53
Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local
Bus ...................................................................................................................... 54
Burst Read and Write Transactions without Wait States, 32-Bit 80960
Local Bus ............................................................................................................ 55
Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ....... 56
Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus57
Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on
Read, 16-Bit 80960 Local Bus ............................................................................ 58
Bus Transactions Generated by Double Word Read Bus Request, Misaligned One
Byte From Quad Word Boundary, 32-Bit 80960 Local Bus................................. 59
HOLD/HOLDA Waveform For Bus Arbitration .................................................... 60
80960 Core Cold Reset Waveform ..................................................................... 61
80960 Local Bus Warm Reset Waveform ........................................................... 62
4
Preliminary
Datasheet
80960VH
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Related Documentation......................................................................................... 7
80960VH Instruction Set .....................................................................................14
Signal Type Definition ......................................................................................... 15
Signal Descriptions.............................................................................................. 16
Power Requirement, Processor Control and Test Signal Descriptions ............... 19
Interrupt Unit Signal Descriptions........................................................................ 20
PCI Signal Descriptions....................................................................................... 21
Memory Controller Signal Descriptions ............................................................... 22
DMA, I
2
C Units Signal Descriptions .................................................................... 24
Clock Related Signals ......................................................................................... 24
PBGA 324 Package Dimensions.........................................................................26
324-Plastic Ball Grid Array Ballout — In Ball Order ............................................ 27
324-Plastic Ball Grid Array Ballout — In Signal Order ........................................30
324-Lead PBGA Package Thermal Characteristics ............................................ 34
Absolute Maximum Ratings................................................................................. 35
Operating Conditions........................................................................................... 35
V
DIFF
Specification for Dual Power Supply Requirements (3.3 V, 5 V) ............... 36
DC Characteristics .............................................................................................. 37
I
CC
Characteristics .............................................................................................. 38
Input Clock Timings............................................................................................. 39
Synchronous Output Timings ..............................................................................39
Synchronous Input Timings................................................................................. 40
Relative Output Timings ...................................................................................... 41
Fast Page Mode Non-interleaved DRAM Output Timings................................... 41
Fast Page Mode Interleaved DRAM Output Timings .......................................... 41
EDO DRAM Output Timings................................................................................ 42
SRAM/ROM Output Timings ............................................................................... 42
Boundary Scan Test Signal Timings ................................................................... 43
I2C Interface Signal Timings ............................................................................... 44
Processor Device ID Register - PDIDR .............................................................. 63
Preliminary
Datasheet
5
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